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Pull requests: llvm/circt

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Pull requests list

[MemoryBanking] Should not overwrite banking factor/dimension when resolving attribute values
#8267 opened Feb 23, 2025 by jiahanxie353 Loading…
[circt-synth] Implemented AIG node balancing algorithm
#8262 opened Feb 21, 2025 by Max-astro Loading…
8
[ImportVerilog]Support the delay control. ImportVerilog Moore
#8259 opened Feb 20, 2025 by hailongSun2000 • Draft
2
[MooreToCore]Remove unexpected observed values for WaitOp. bug Something isn't working Moore
#8255 opened Feb 19, 2025 by hailongSun2000 Loading…
5
[Transforms][circt-synth] Add HierarchicalRunner pass
#8254 opened Feb 18, 2025 by uenoku Loading…
[LLHD] Add dedicated Mem2Reg pass LLHD
#8244 opened Feb 15, 2025 by fabianschuiki Loading…
2
1
[Python] Declare a separate sub-target for support sources
#8243 opened Feb 14, 2025 by maerhart Loading…
[circt-verilog-lsp-server] Add Verilog Language Server
#8234 opened Feb 13, 2025 by uenoku Loading…
[LLHD][TCM] Fix CFG loops detection
#8230 opened Feb 12, 2025 by AndreyVV-100 Loading…
1
[arcilator] Add missing install configuration for arcilator-runtime.h and arcilator-header-cpp.py
#8223 opened Feb 11, 2025 by FurryAcetylCoA Loading…
[circt-synth] Partially lower Comb operations and run canonicalizations
#8218 opened Feb 10, 2025 by uenoku Loading…
[Pipeline] Extend Pipeline Dialect's pipeline-schedule-linear pass to support more types of scheduling problems
#8209 opened Feb 8, 2025 by bubblepipe42 Loading…
[ESI][BSP] Simple ToHost DMA engine ESI
#8207 opened Feb 7, 2025 by teqdruid • Draft
[MooreToCore] Properly deal with OOB access in dyn_extract Moore
#8201 opened Feb 7, 2025 by maerhart Loading…
13
[FIRRTL] Add Clock Switch intrinsic
#8183 opened Feb 3, 2025 by darthscsi • Draft
1
[COMB] Get rid of "bin" flag in comb.
#8180 opened Feb 3, 2025 by darthscsi • Draft
3
[HW] Start of high imedence operations and types
#8134 opened Jan 28, 2025 by darthscsi Loading…
6
[FIRRTL][CAPI] add layer for firrtlTypeGetRef
#8093 opened Jan 17, 2025 by sequencer Loading…
[RTG][python] fix populateDialectRTGTestSubmodule namespacing
#8078 opened Jan 13, 2025 by makslevental Loading…
4
[HW] Add passes to remove modules from the hierarchy and recursively expose IO of their instances
#8070 opened Jan 12, 2025 by CircuitCoder Loading…
1 task
6
Convert ICE40 to BLIF
#8031 opened Jan 5, 2025 by darthscsi • Draft
Add the BLIF dialect.
#8019 opened Dec 29, 2024 by darthscsi Loading…
4
Add the ICE40 dialect.
#8018 opened Dec 27, 2024 by darthscsi Loading…
11
[ImportVerilog] Support for Procedural assign statements ImportVerilog Moore
#8010 opened Dec 19, 2024 by owlxiao Loading…
5
[HW] Add pass to outline certain ops: hw-outline-ops HW Involving the `hw` dialect
#7991 opened Dec 13, 2024 by teqdruid Loading…
15
ProTip! What’s not been updated in a month: updated:<2025-01-23.