[CIR][Lowering][debuginfo] Disable debug info if -g is not specified

clang/include/clang/CIR/LowerToLLVM.h

@@ -31,7 +31,8 @@ namespace cir {
 namespace direct {
 std::unique_ptr<llvm::Module> lowerDirectlyFromCIRToLLVMIR(
     mlir::ModuleOp theModule, llvm::LLVMContext &llvmCtx,
-    bool disableVerifier = false, bool disableCCLowering = false);
+    bool disableVerifier = false, bool disableCCLowering = false,
+    bool disableDebugInfo = false);
 }
 
 // Lower directly from pristine CIR to LLVMIR.

clang/lib/CIR/FrontendAction/CIRGenAction.cpp

@@ -94,10 +94,11 @@ getBackendActionFromOutputType(CIRGenAction::OutputType action) {
 static std::unique_ptr<llvm::Module> lowerFromCIRToLLVMIR(
     const clang::FrontendOptions &feOptions, mlir::ModuleOp mlirMod,
     std::unique_ptr<mlir::MLIRContext> mlirCtx, llvm::LLVMContext &llvmCtx,
-    bool disableVerifier = false, bool disableCCLowering = false) {
+    bool disableVerifier = false, bool disableCCLowering = false,
+    bool disableDebugInfo = false) {
   if (feOptions.ClangIRDirectLowering)
     return direct::lowerDirectlyFromCIRToLLVMIR(
-        mlirMod, llvmCtx, disableVerifier, disableCCLowering);
+        mlirMod, llvmCtx, disableVerifier, disableCCLowering, disableDebugInfo);
   else
     return lowerFromCIRToMLIRToLLVMIR(mlirMod, std::move(mlirCtx), llvmCtx);
 }
@@ -284,10 +285,12 @@ class CIRGenConsumer : public clang::ASTConsumer {
     case CIRGenAction::OutputType::EmitObj:
     case CIRGenAction::OutputType::EmitAssembly: {
       llvm::LLVMContext llvmCtx;
-      auto llvmModule =
-          lowerFromCIRToLLVMIR(feOptions, mlirMod, std::move(mlirCtx), llvmCtx,
-                               feOptions.ClangIRDisableCIRVerifier,
-                               !feOptions.ClangIRCallConvLowering);
+      bool disableDebugInfo =
+          codeGenOptions.getDebugInfo() == llvm::codegenoptions::NoDebugInfo;
+      auto llvmModule = lowerFromCIRToLLVMIR(
+          feOptions, mlirMod, std::move(mlirCtx), llvmCtx,
+          feOptions.ClangIRDisableCIRVerifier,
+          !feOptions.ClangIRCallConvLowering, disableDebugInfo);
 
       BackendAction backendAction = getBackendActionFromOutputType(action);
 
@@ -436,10 +439,12 @@ void CIRGenAction::ExecuteAction() {
 
   // FIXME(cir): This compilation path does not account for some flags.
   llvm::LLVMContext llvmCtx;
+  bool disableDebugInfo =
+      ci.getCodeGenOpts().getDebugInfo() == llvm::codegenoptions::NoDebugInfo;
   auto llvmModule = lowerFromCIRToLLVMIR(
       ci.getFrontendOpts(), mlirModule.release(),
       std::unique_ptr<mlir::MLIRContext>(mlirContext), llvmCtx,
-      /*disableVerifier=*/false, /*disableCCLowering=*/true);
+      /*disableVerifier=*/false, /*disableCCLowering=*/true, disableDebugInfo);
 
   if (outstream)
     llvmModule->print(*outstream, nullptr);
@@ -479,7 +484,8 @@ EmitObjAction::EmitObjAction(mlir::MLIRContext *_MLIRContext)
     : CIRGenAction(OutputType::EmitObj, _MLIRContext) {}
 } // namespace cir
 
-// Used for -fclangir-analysis-only: use CIR analysis but still use original LLVM codegen path
+// Used for -fclangir-analysis-only: use CIR analysis but still use original
+// LLVM codegen path
 void AnalysisOnlyActionBase::anchor() {}
 AnalysisOnlyActionBase::AnalysisOnlyActionBase(unsigned _Act,
                                                llvm::LLVMContext *_VMContext)

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

@@ -4402,7 +4402,8 @@ extern void registerCIRDialectTranslation(mlir::MLIRContext &context);
 
 std::unique_ptr<llvm::Module>
 lowerDirectlyFromCIRToLLVMIR(mlir::ModuleOp theModule, LLVMContext &llvmCtx,
-                             bool disableVerifier, bool disableCCLowering) {
+                             bool disableVerifier, bool disableCCLowering,
+                             bool disableDebugInfo) {
   llvm::TimeTraceScope scope("lower from CIR to LLVM directly");
 
   mlir::MLIRContext *mlirCtx = theModule.getContext();
@@ -4412,8 +4413,9 @@ lowerDirectlyFromCIRToLLVMIR(mlir::ModuleOp theModule, LLVMContext &llvmCtx,
   // This is necessary to have line tables emitted and basic
   // debugger working. In the future we will add proper debug information
   // emission directly from our frontend.
-  pm.addPass(mlir::LLVM::createDIScopeForLLVMFuncOpPass());
-
+  if (!disableDebugInfo) {
+    pm.addPass(mlir::LLVM::createDIScopeForLLVMFuncOpPass());
+  }
   // FIXME(cir): this shouldn't be necessary. It's meant to be a temporary
   // workaround until we understand why some unrealized casts are being
   // emmited and how to properly avoid them.

clang/test/CIR/CodeGen/AArch64/neon.c

@@ -10156,7 +10156,7 @@ uint8x16_t test_vld1q_u8(uint8_t const *a) {
   // CIR: cir.load align(1) %[[CAST]] : !cir.ptr<!cir.vector<!u8i x 16>>, !cir.vector<!u8i x 16>
 
   // LLVM-LABEL: @test_vld1q_u8
-  // LLVM:   [[TMP1:%.*]] = load <16 x i8>, ptr %0, align 1,
+  // LLVM:   [[TMP1:%.*]] = load <16 x i8>, ptr %0, align 1
 }
 
 uint16x8_t test_vld1q_u16(uint16_t const *a) {
@@ -10166,7 +10166,7 @@ uint16x8_t test_vld1q_u16(uint16_t const *a) {
   // CIR: cir.load align(2) %[[CAST]] : !cir.ptr<!cir.vector<!u16i x 8>>, !cir.vector<!u16i x 8>
 
   // LLVM-LABEL: @test_vld1q_u16
-  // LLVM:   [[TMP1:%.*]] = load <8 x i16>, ptr %0, align 2,
+  // LLVM:   [[TMP1:%.*]] = load <8 x i16>, ptr %0, align 2
 }
 
 uint32x4_t test_vld1q_u32(uint32_t const *a) {
@@ -10176,7 +10176,7 @@ uint32x4_t test_vld1q_u32(uint32_t const *a) {
   // CIR: cir.load align(4) %[[CAST]] : !cir.ptr<!cir.vector<!u32i x 4>>, !cir.vector<!u32i x 4>
 
   // LLVM-LABEL: @test_vld1q_u32
-  // LLVM:   [[TMP1:%.*]] = load <4 x i32>, ptr %0, align 4,
+  // LLVM:   [[TMP1:%.*]] = load <4 x i32>, ptr %0, align 4
 }
 
 uint64x2_t test_vld1q_u64(uint64_t const *a) {
@@ -10186,7 +10186,7 @@ uint64x2_t test_vld1q_u64(uint64_t const *a) {
   // CIR: cir.load align(8) %[[CAST]] : !cir.ptr<!cir.vector<!u64i x 2>>, !cir.vector<!u64i x 2>
 
   // LLVM-LABEL: @test_vld1q_u64
-  // LLVM:   [[TMP1:%.*]] = load <2 x i64>, ptr %0, align 8,
+  // LLVM:   [[TMP1:%.*]] = load <2 x i64>, ptr %0, align 8
 }
 
 int8x16_t test_vld1q_s8(int8_t const *a) {
@@ -10196,7 +10196,7 @@ int8x16_t test_vld1q_s8(int8_t const *a) {
   // CIR: cir.load align(1) %[[CAST]] : !cir.ptr<!cir.vector<!s8i x 16>>, !cir.vector<!s8i x 16>
 
   // LLVM-LABEL: @test_vld1q_s8
-  // LLVM:   [[TMP1:%.*]] = load <16 x i8>, ptr %0, align 1,
+  // LLVM:   [[TMP1:%.*]] = load <16 x i8>, ptr %0, align 1
 }
 
 int16x8_t test_vld1q_s16(int16_t const *a) {
@@ -10206,7 +10206,7 @@ int16x8_t test_vld1q_s16(int16_t const *a) {
   // CIR: cir.load align(2) %[[CAST]] : !cir.ptr<!cir.vector<!s16i x 8>>, !cir.vector<!s16i x 8>
 
   // LLVM-LABEL: @test_vld1q_s16
-  // LLVM:   [[TMP1:%.*]] = load <8 x i16>, ptr %0, align 2,
+  // LLVM:   [[TMP1:%.*]] = load <8 x i16>, ptr %0, align 2
 }
 
 int32x4_t test_vld1q_s32(int32_t const *a) {
@@ -10216,7 +10216,7 @@ int32x4_t test_vld1q_s32(int32_t const *a) {
   // CIR: cir.load align(4) %[[CAST]] : !cir.ptr<!cir.vector<!s32i x 4>>, !cir.vector<!s32i x 4>
 
   // LLVM-LABEL: @test_vld1q_s32
-  // LLVM:   [[TMP1:%.*]] = load <4 x i32>, ptr %0, align 4,
+  // LLVM:   [[TMP1:%.*]] = load <4 x i32>, ptr %0, align 4
 }
 
 int64x2_t test_vld1q_s64(int64_t const *a) {
@@ -10226,7 +10226,7 @@ int64x2_t test_vld1q_s64(int64_t const *a) {
   // CIR: cir.load align(8) %[[CAST]] : !cir.ptr<!cir.vector<!s64i x 2>>, !cir.vector<!s64i x 2>
 
   // LLVM-LABEL: @test_vld1q_s64
-  // LLVM:   [[TMP1:%.*]] = load <2 x i64>, ptr %0, align 8,
+  // LLVM:   [[TMP1:%.*]] = load <2 x i64>, ptr %0, align 8
 }
 
 // NYI-LABEL: @test_vld1q_f16(
@@ -11389,7 +11389,7 @@ void test_vst1q_u8(uint8_t *a, uint8x16_t b) {
   // CIR: cir.store align(1) %{{.*}}, %[[CAST]] : !cir.vector<!u8i x 16>, !cir.ptr<!cir.vector<!u8i x 16>>
 
   // LLVM-LABEL: @test_vst1q_u8
-  // LLVM:   store <16 x i8> %{{.*}}, ptr %0, align 1,
+  // LLVM:   store <16 x i8> %{{.*}}, ptr %0, align 1
 }
 
 void test_vst1q_u16(uint16_t *a, uint16x8_t b) {
@@ -11399,7 +11399,7 @@ void test_vst1q_u16(uint16_t *a, uint16x8_t b) {
   // CIR: cir.store align(2) %{{.*}}, %[[CAST]] : !cir.vector<!u16i x 8>, !cir.ptr<!cir.vector<!u16i x 8>>
 
   // LLVM-LABEL: @test_vst1q_u16
-  // LLVM:   store <8 x i16> %{{.*}}, ptr %0, align 2,
+  // LLVM:   store <8 x i16> %{{.*}}, ptr %0, align 2
 }
 
 void test_vst1q_u32(uint32_t *a, uint32x4_t b) {
@@ -11409,7 +11409,7 @@ void test_vst1q_u32(uint32_t *a, uint32x4_t b) {
   // CIR: cir.store align(4) %{{.*}}, %[[CAST]] : !cir.vector<!u32i x 4>, !cir.ptr<!cir.vector<!u32i x 4>>
 
   // LLVM-LABEL: @test_vst1q_u32
-  // LLVM:   store <4 x i32> %{{.*}}, ptr %0, align 4,
+  // LLVM:   store <4 x i32> %{{.*}}, ptr %0, align 4
 }
 
 void test_vst1q_u64(uint64_t *a, uint64x2_t b) {
@@ -11419,7 +11419,7 @@ void test_vst1q_u64(uint64_t *a, uint64x2_t b) {
   // CIR: cir.store align(8) %{{.*}}, %[[CAST]] : !cir.vector<!u64i x 2>, !cir.ptr<!cir.vector<!u64i x 2>>
 
   // LLVM-LABEL: @test_vst1q_u64
-  // LLVM:   store <2 x i64> %{{.*}}, ptr %0, align 8,
+  // LLVM:   store <2 x i64> %{{.*}}, ptr %0, align 8
 }
 
 void test_vst1q_s8(int8_t *a, int8x16_t b) {
@@ -11429,7 +11429,7 @@ void test_vst1q_s8(int8_t *a, int8x16_t b) {
   // CIR: cir.store align(1) %{{.*}}, %[[CAST]] : !cir.vector<!s8i x 16>, !cir.ptr<!cir.vector<!s8i x 16>>
 
   // LLVM-LABEL: @test_vst1q_s8
-  // LLVM:   store <16 x i8> %{{.*}}, ptr %0, align 1,
+  // LLVM:   store <16 x i8> %{{.*}}, ptr %0, align 1
 }
 
 void test_vst1q_s16(int16_t *a, int16x8_t b) {
@@ -11439,7 +11439,7 @@ void test_vst1q_s16(int16_t *a, int16x8_t b) {
   // CIR: cir.store align(2) %{{.*}}, %[[CAST]] : !cir.vector<!s16i x 8>, !cir.ptr<!cir.vector<!s16i x 8>>
 
   // LLVM-LABEL: @test_vst1q_s16
-  // LLVM:   store <8 x i16> %{{.*}}, ptr %0, align 2,
+  // LLVM:   store <8 x i16> %{{.*}}, ptr %0, align 2
 }
 
 void test_vst1q_s32(int32_t *a, int32x4_t b) {
@@ -11449,7 +11449,7 @@ void test_vst1q_s32(int32_t *a, int32x4_t b) {
   // CIR: cir.store align(4) %{{.*}}, %[[CAST]] : !cir.vector<!s32i x 4>, !cir.ptr<!cir.vector<!s32i x 4>>
 
   // LLVM-LABEL: @test_vst1q_s32
-  // LLVM:   store <4 x i32> %{{.*}}, ptr %0, align 4,
+  // LLVM:   store <4 x i32> %{{.*}}, ptr %0, align 4
 }
 
 void test_vst1q_s64(int64_t *a, int64x2_t b) {
@@ -11459,7 +11459,7 @@ void test_vst1q_s64(int64_t *a, int64x2_t b) {
   // CIR: cir.store align(8) %{{.*}}, %[[CAST]] : !cir.vector<!s64i x 2>, !cir.ptr<!cir.vector<!s64i x 2>>
 
   // LLVM-LABEL: @test_vst1q_s64
-  // LLVM:   store <2 x i64> %{{.*}}, ptr %0, align 8,
+  // LLVM:   store <2 x i64> %{{.*}}, ptr %0, align 8
 }
 
 // NYI-LABEL: @test_vst1q_f16(

clang/test/CIR/CodeGen/OpenCL/convergent.cl

@@ -21,10 +21,10 @@ void non_convfun(void) {
 // External functions should be assumed convergent.
 void f(void);
 // CIR: cir.func{{.+}} @f(){{.*}} extra(#fn_attr[[CONV_DECL_ATTR]])
-// LLVM: declare {{.+}} spir_func void @f() local_unnamed_addr #[[CONV_ATTR:[0-9]+]]
+// LLVM: declare spir_func void @f() local_unnamed_addr #[[CONV_ATTR:[0-9]+]]
 void g(void);
 // CIR: cir.func{{.+}} @g(){{.*}} extra(#fn_attr[[CONV_DECL_ATTR]])
-// LLVM: declare {{.+}} spir_func void @g() local_unnamed_addr #[[CONV_ATTR]]
+// LLVM: declare spir_func void @g() local_unnamed_addr #[[CONV_ATTR]]
 
 // Test two if's are merged and non_convfun duplicated.
 void test_merge_if(int a) {
@@ -68,7 +68,7 @@ void test_merge_if(int a) {
 
 void convfun(void) __attribute__((convergent));
 // CIR: cir.func{{.+}} @convfun(){{.*}} extra(#fn_attr[[CONV_DECL_ATTR]])
-// LLVM: declare {{.+}} spir_func void @convfun() local_unnamed_addr #[[CONV_ATTR]]
+// LLVM: declare spir_func void @convfun() local_unnamed_addr #[[CONV_ATTR]]
 
 // Test two if's are not merged.
 void test_no_merge_if(int a) {

clang/test/CIR/CodeGen/abstract-cond.c

@@ -26,7 +26,7 @@ int f6(int a0, struct s6 a1, struct s6 a2) {
 // LLVM-LABEL: @f6
 // LLVM:    %[[LOAD_A0:.*]] = load i32, ptr {{.*}}
 // LLVM:    %[[COND:.*]] = icmp ne i32 %[[LOAD_A0]], 0
-// LLVM:    br i1 %[[COND]], label %[[A1_PATH:.*]], label %[[A2_PATH:.*]],
+// LLVM:    br i1 %[[COND]], label %[[A1_PATH:.*]], label %[[A2_PATH:.*]]
 // LLVM:  [[A1_PATH]]:
 // LLVM:    call void @llvm.memcpy.p0.p0.i32(ptr %[[TMP:.*]], ptr {{.*}}, i32 4, i1 false)
 // LLVM:    br label %[[EXIT:[a-z0-9]+]]

clang/test/CIR/CodeGen/annotations-var.c

@@ -37,5 +37,5 @@ void local(void) {
 // LLVM: call void @llvm.var.annotation.p0.p0(ptr %[[ALLOC2]], ptr @.str.annotation, ptr @.str.1.annotation, i32 24, ptr null)
 // LLVM: %[[ALLOC3:.*]] = alloca i32
 // LLVM: call void @llvm.var.annotation.p0.p0(ptr %[[ALLOC3]], ptr @.str.3.annotation, 
-// LLVM-SAME: ptr @.str.1.annotation, i32 25, ptr @.args.annotation),
+// LLVM-SAME: ptr @.str.1.annotation, i32 25, ptr @.args.annotation)
 }

clang/test/CIR/CodeGen/atomic-xchg-field.c

@@ -58,11 +58,11 @@ void structAtomicExchange(unsigned referenceCount, wPtr item) {
 // LLVM:   %[[RES:.*]] = cmpxchg weak ptr %9, i32 %[[EXP]], i32 %[[DES]] seq_cst seq_cst
 // LLVM:   %[[OLD:.*]] = extractvalue { i32, i1 } %[[RES]], 0
 // LLVM:   %[[CMP:.*]] = extractvalue { i32, i1 } %[[RES]], 1
-// LLVM:   %[[Z:.*]] = zext i1 %[[CMP]] to i8, !dbg !16
-// LLVM:   %[[X:.*]] = xor i8 %[[Z]], 1, !dbg !16
-// LLVM:   %[[FAIL:.*]] = trunc i8 %[[X]] to i1, !dbg !16
+// LLVM:   %[[Z:.*]] = zext i1 %[[CMP]] to i8
+// LLVM:   %[[X:.*]] = xor i8 %[[Z]], 1
+// LLVM:   %[[FAIL:.*]] = trunc i8 %[[X]] to i1
 
-// LLVM:   br i1 %[[FAIL:.*]], label %[[STORE_OLD:.*]], label %[[CONTINUE:.*]],
+// LLVM:   br i1 %[[FAIL:.*]], label %[[STORE_OLD:.*]], label %[[CONTINUE:.*]]
 // LLVM: [[STORE_OLD]]:
 // LLVM:   store i32 %[[OLD]], ptr
 // LLVM:   br label %[[CONTINUE]]

clang/test/CIR/CodeGen/call-via-class-member-funcptr.cpp

@@ -38,17 +38,17 @@ void fn1() { f f1; }
 // LLVM: %class.f = type { %class.a }
 // LLVM:  %class.a = type { i8 }
 // LLVM: @h = global i32 0
-// LLVM: declare {{.*}} ptr @_ZN1a1bEi(i32)
+// LLVM: declare ptr @_ZN1a1bEi(i32)
 
 // LLVM: define dso_local ptr @_ZN1f1bEv(ptr [[ARG0:%.*]])
 // LLVM: [[ARG0_SAVE:%.*]] = alloca ptr, i64 1, align 8
 // LLVM: [[RET_SAVE:%.*]] = alloca ptr, i64 1, align 8
-// LLVM: store ptr [[ARG0]], ptr [[ARG0_SAVE]], align 8,
+// LLVM: store ptr [[ARG0]], ptr [[ARG0_SAVE]], align 8
 // LLVM: [[ARG0_LOAD:%.*]] = load ptr, ptr [[ARG0_SAVE]], align 8
-// LLVM: [[FUNC_PTR:%.*]] = getelementptr %class.f, ptr [[ARG0_LOAD]], i32 0, i32 0,
+// LLVM: [[FUNC_PTR:%.*]] = getelementptr %class.f, ptr [[ARG0_LOAD]], i32 0, i32 0
 // LLVM: [[VAR_H:%.*]] = load i32, ptr @h, align 4
-// LLVM: [[RET_VAL:%.*]] = call ptr @_ZN1a1bEi(i32 [[VAR_H]]),
-// LLVM: store ptr [[RET_VAL]], ptr [[RET_SAVE]], align 8,
+// LLVM: [[RET_VAL:%.*]] = call ptr @_ZN1a1bEi(i32 [[VAR_H]])
+// LLVM: store ptr [[RET_VAL]], ptr [[RET_SAVE]], align 8
 // LLVM: [[RET_VAL2:%.*]] = load ptr, ptr [[RET_SAVE]], align 8
 // LLVM: ret ptr [[RET_VAL2]]
 

clang/test/CIR/CodeGen/clear_cache.c

@@ -20,7 +20,7 @@ char buffer[32] = "This is a largely unused buffer";
 // CIR:  cir.clear_cache %[[VAL_3]] : !cir.ptr<!void>, %[[VAL_8]],
 
 // LLVM-LABEL: main
-// LLVM:  call void @llvm.clear_cache(ptr @buffer, ptr getelementptr (i8, ptr @buffer, i64 32)),
+// LLVM:  call void @llvm.clear_cache(ptr @buffer, ptr getelementptr (i8, ptr @buffer, i64 32))
 
 int main(void) {
   __builtin___clear_cache(buffer, buffer+32);

clang/test/CIR/CodeGen/fun-ptr.c

@@ -61,7 +61,7 @@ int foo(Data* d) {
 // CIR:    cir.call [[RET]]() : (!cir.ptr<!cir.func<!void ()>>) -> ()
 // CIR:    cir.return
 
-// LLVM: declare {{.*}} ptr {{@.*test.*}}()
+// LLVM: declare ptr {{@.*test.*}}()
 // LLVM: define dso_local void {{@.*bar.*}}()
 // LLVM:   [[RET:%.*]] = call ptr {{@.*test.*}}()
 // LLVM:   call void [[RET]]()

clang/test/CIR/CodeGen/func_dsolocal_pie.c

@@ -22,13 +22,13 @@ int main() {
 // CIR: cir.call @foo([[TMP1]]) : (!s32i) -> ()
 
 // LLVM: define dso_local void @foo(i32 [[TMP3:%.*]])
-// LLVM: [[ARG_STACK:%.*]] = alloca i32, i64 1, align 4,
+// LLVM: [[ARG_STACK:%.*]] = alloca i32, i64 1, align 4
 // LLVM: store i32 [[TMP3]], ptr [[ARG_STACK]], align 4
-// LLVM: ret void,
+// LLVM: ret void
 
 // LLVM: define dso_local i32 @main()
-// LLVM: [[TMP4:%.*]] = alloca i32, i64 1, align 4,
-// LLVM: call void @foo(i32 2),
+// LLVM: [[TMP4:%.*]] = alloca i32, i64 1, align 4
+// LLVM: call void @foo(i32 2)
 // LLVM: store i32 0, ptr [[TMP4]], align 4
 // LLVM: [[RET_VAL:%.*]] = load i32, ptr [[TMP4]], align 4
-// LLVM: ret i32 [[RET_VAL]],
+// LLVM: ret i32 [[RET_VAL]]

clang/test/CIR/CodeGen/global-new.cpp

@@ -45,20 +45,20 @@ e *g = new e(0);
 
 // LLVM_EH: define internal void @__cxx_global_var_init() personality ptr @__gxx_personality_v0
 // LLVM_EH:   call ptr @_Znwm(i64 1)
-// LLVM_EH:   br label %[[L2:.*]],
+// LLVM_EH:   br label %[[L2:.*]]
 
 // LLVM_EH: [[L2]]:
 // LLVM_EH:   invoke void @_ZN1eC1Ei
-// LLVM_EH:           to label %[[CONT:.*]] unwind label %[[PAD:.*]],
+// LLVM_EH:           to label %[[CONT:.*]] unwind label %[[PAD:.*]]
 
 // LLVM_EH: [[CONT]]:
-// LLVM_EH:   br label %[[END:.*]],
+// LLVM_EH:   br label %[[END:.*]]
 
 // LLVM_EH: [[PAD]]:
 // LLVM_EH:   landingpad { ptr, i32 }
 // LLVM_EH:      cleanup
 // LLVM_EH:   call void @_ZdlPvm
-// LLVM_EH:   br label %[[RESUME:.*]],
+// LLVM_EH:   br label %[[RESUME:.*]]
 
 // LLVM_EH: [[RESUME]]:
 // LLVM_EH:   resume { ptr, i32 }