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[CIR] Always zero-extend shift amounts #1568

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Merged
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Apr 17, 2025
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[CIR] Always zero-extend shift amounts #1568

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5 changes: 3 additions & 2 deletions clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2967,10 +2967,11 @@ mlir::LogicalResult CIRToLLVMShiftOpLowering::matchAndRewrite(
// behavior might occur in the casts below as per [C99 6.5.7.3].
// Vector type shift amount needs no cast as type consistency is expected to
// be already be enforced at CIRGen.
// Negative shift amounts are undefined behavior so we can always zero extend
// the integer here.
if (cirAmtTy)
amt = getLLVMIntCast(rewriter, amt, mlir::cast<mlir::IntegerType>(llvmTy),
!cirAmtTy.isSigned(), cirAmtTy.getWidth(),
cirValTy.getWidth());
true, cirAmtTy.getWidth(), cirValTy.getWidth());

// Lower to the proper LLVM shift operation.
if (op.getIsShiftleft())
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2 changes: 1 addition & 1 deletion clang/test/CIR/Lowering/shift.cir
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Expand Up @@ -16,7 +16,7 @@ module {

// Should allow shift with signed smaller amount type.
%2 = cir.shift(left, %arg1 : !s32i, %arg0 : !s16i) -> !s32i
// CHECK: %[[#CAST:]] = llvm.sext %{{.+}} : i16 to i32
// CHECK: %[[#CAST:]] = llvm.zext %{{.+}} : i16 to i32
// CHECK: llvm.shl %{{.+}}, %[[#CAST]] : i32

// Should allow shift with unsigned smaller amount type.
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