Skip to content

[CIR][Codegen] supports aarch64_be #864

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Sep 19, 2024
Merged

[CIR][Codegen] supports aarch64_be #864

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
fb2be8b
[CIR][Codegen] aarch64 big endian
gitoleg Sep 19, 2024
85c7dd3
minor
gitoleg Sep 19, 2024
8fa5a3a
clang-format ...
gitoleg Sep 19, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@
#ifndef LLVM_CLANG_CIR_DIALECT_IR_CIRDATALAYOUT_H
#define LLVM_CLANG_CIR_DIALECT_IR_CIRDATALAYOUT_H

#include "mlir/Dialect/DLTI/DLTI.h"
#include "mlir/IR/BuiltinOps.h"
#include "clang/CIR/Dialect/IR/CIRTypes.h"
#include "llvm/IR/DataLayout.h"
Expand Down Expand Up @@ -41,7 +42,7 @@ class CIRDataLayout {
CIRDataLayout(mlir::ModuleOp modOp);

/// Parse a data layout string (with fallback to default values).
void reset();
void reset(mlir::DataLayoutSpecInterface spec);

// Free all internal data structures.
void clear();
Expand Down
2 changes: 2 additions & 0 deletions clang/lib/CIR/CodeGen/TargetInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -588,6 +588,8 @@ const TargetCIRGenInfo &CIRGenModule::getTargetCIRGenInfo() {
switch (Triple.getArch()) {
default:
assert(false && "Target not yet supported!");

case llvm::Triple::aarch64_be:
case llvm::Triple::aarch64: {
AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
assert(getTarget().getABI() == "aapcs" ||
Expand Down
17 changes: 14 additions & 3 deletions clang/lib/CIR/Dialect/IR/CIRDataLayout.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -110,13 +110,24 @@ class StructLayoutMap {

} // namespace

CIRDataLayout::CIRDataLayout(mlir::ModuleOp modOp) : layout{modOp} { reset(); }
CIRDataLayout::CIRDataLayout(mlir::ModuleOp modOp) : layout{modOp} {
reset(modOp.getDataLayoutSpec());
}

void CIRDataLayout::reset() {
void CIRDataLayout::reset(mlir::DataLayoutSpecInterface spec) {
clear();

LayoutMap = nullptr;
bigEndian = false;
if (spec) {
auto key = mlir::StringAttr::get(
spec.getContext(), mlir::DLTIDialect::kDataLayoutEndiannessKey);
if (auto entry = spec.getSpecForIdentifier(key))
if (auto str = llvm::dyn_cast<mlir::StringAttr>(entry.getValue()))
bigEndian = str == mlir::DLTIDialect::kDataLayoutEndiannessBig;
}

LayoutMap = nullptr;

// ManglingMode = MM_None;
// NonIntegralAddressSpaces.clear();
StructAlignment =
Expand Down
1 change: 1 addition & 0 deletions clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,7 @@ createTargetLoweringInfo(LowerModule &LM) {
const llvm::Triple &Triple = Target.getTriple();

switch (Triple.getArch()) {
case llvm::Triple::aarch64_be:
case llvm::Triple::aarch64: {
AArch64ABIKind Kind = AArch64ABIKind::AAPCS;
if (Target.getABI() == "darwinpcs")
Expand Down
54 changes: 54 additions & 0 deletions clang/test/CIR/CodeGen/bitfields_be.c
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,54 @@
// RUN: %clang_cc1 -triple aarch64_be-unknown-linux-gnu -emit-llvm %s -o %t.cir
// RUN: FileCheck --input-file=%t.cir %s -check-prefix=LLVM

// RUN: %clang_cc1 -triple aarch64_be-unknown-linux-gnu -fclangir -emit-llvm %s -o %t1.cir
// RUN: FileCheck --input-file=%t1.cir %s

typedef struct {
int a : 4;
int b : 11;
int c : 17;
} S;

void init(S* s) {
s->a = -4;
s->b = 42;
s->c = -12345;
}

// field 'a'
// LLVM: %[[PTR0:.*]] = load ptr
// CHECK: %[[PTR0:.*]] = load ptr
// LLVM: %[[VAL0:.*]] = load i32, ptr %[[PTR0]]
// CHECK: %[[VAL0:.*]] = load i32, ptr %[[PTR0]]
// LLVM: %[[AND0:.*]] = and i32 %[[VAL0]], 268435455
// CHECK: %[[AND0:.*]] = and i32 %[[VAL0]], 268435455
// LLVM: %[[OR0:.*]] = or i32 %[[AND0]], -1073741824
// CHECK: %[[OR0:.*]] = or i32 %[[AND0]], -1073741824
// LLVM: store i32 %[[OR0]], ptr %[[PTR0]]
// CHECK: store i32 %[[OR0]], ptr %[[PTR0]]

// field 'b'
// LLVM: %[[PTR1:.*]] = load ptr
// CHECK: %[[PTR1:.*]] = load ptr
// LLVM: %[[VAL1:.*]] = load i32, ptr %[[PTR1]]
// CHECK: %[[VAL1:.*]] = load i32, ptr %[[PTR1]]
// LLVM: %[[AND1:.*]] = and i32 %[[VAL1]], -268304385
// CHECK: %[[AND1:.*]] = and i32 %[[VAL1]], -268304385
// LLVM: %[[OR1:.*]] = or i32 %[[AND1]], 5505024
// CHECK: %[[OR1:.*]] = or i32 %[[AND1]], 5505024
// LLVM: store i32 %[[OR1]], ptr %[[PTR1]]
// CHECK: store i32 %[[OR1]], ptr %[[PTR1]]

// field 'c'
// LLVM: %[[PTR2:.*]] = load ptr
// CHECK: %[[PTR2:.*]] = load ptr
// LLVM: %[[VAL2:.*]] = load i32, ptr %[[PTR2]]
// CHECK: %[[VAL2:.*]] = load i32, ptr %[[PTR2]]
// LLVM: %[[AND2:.*]] = and i32 %[[VAL2]], -131072
// CHECK: %[[AND2:.*]] = and i32 %[[VAL2]], -131072
// LLVM: %[[OR2:.*]] = or i32 %[[AND2]], 118727
// CHECK: %[[OR2:.*]] = or i32 %[[AND2]], 118727
// LLVM: store i32 %[[OR2]], ptr %[[PTR2]]
// CHECK: store i32 %[[OR2]], ptr %[[PTR2]]

Loading