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llvm · Aug 15, 2024 · 12778c3 · 12778c3
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commit 12778c3
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Showing 4 changed files with 3 additions and 5 deletions.
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
@@ -111,6 +111,7 @@ Changes to the RISC-V Backend
 * Fixed length vector support using RVV instructions now requires VLEN>=64. This
   means Zve32x and Zve32f will also require Zvl64b. The prior support was
   largely untested.
+* The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally.
 
 Changes to the WebAssembly Backend
 ----------------------------------

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -757,9 +757,6 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
 def FeatureStdExtZvbc32e
     : RISCVExperimentalExtension<"zvbc32e", 0, 7,
                                  "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)">;
-def HasStdExtZvbc32e : Predicate<"Subtarget->hasStdExtZvbc32e()">,
-                       AssemblerPredicate<(all_of FeatureStdExtZvbc32e),
-                        "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)">;
 
 def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">,
                              AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e),

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -150,7 +150,7 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
                  SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
 } // Predicates = [HasStdExtZvkg]
 
-let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {
+let Predicates = [HasStdExtZvkgs], RVVConstraint = VS2Constraint in {
   def VGHSH_VS : PALUVVNoVmTernary<0b100011, OPMVV, "vghsh.vs">,
                  SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",
                                 "ReadVGHSHV">;

diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -752,7 +752,7 @@ Error RISCVISAInfo::checkDependency() {
 
   if (Exts.count("zvbc32e") && !Exts.count("zve32x"))
     return getError(
-        "'zvbc32e' requires 'v' or 'zve32*' extension to also be specified");
+        "'zvbc32e' requires 'v' or 'zve*' extension to also be specified");
 
   if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkgs") ||
        Exts.count("zvkned") || Exts.count("zvknha") || Exts.count("zvksed") ||