remove init vec

Author: fhossein-quic

llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp

@@ -58,6 +58,7 @@
 // are PHI inst.
 //
 //===----------------------------------------------------------------------===//
+#include <unordered_set>
 #define HEXAGON_QFP_OPTIMIZER "QFP optimizer pass"
 
 #include "Hexagon.h"
@@ -86,21 +87,7 @@ cl::opt<bool>
     DisableQFOptimizer("disable-qfp-opt", cl::init(false),
                        cl::desc("Disable optimization of Qfloat operations."));
 
-namespace{
-const std::vector<unsigned short> QFPInst = {
-    Hexagon::V6_vadd_hf,          Hexagon::V6_vadd_qf16,
-    Hexagon::V6_vadd_qf16_mix,    Hexagon::V6_vadd_qf32,
-    Hexagon::V6_vadd_qf32_mix,    Hexagon::V6_vadd_sf,
-    Hexagon::V6_vconv_hf_qf16,    Hexagon::V6_vconv_hf_qf32,
-    Hexagon::V6_vconv_sf_qf32,    Hexagon::V6_vmpy_qf16,
-    Hexagon::V6_vmpy_qf16_hf,     Hexagon::V6_vmpy_qf16_mix_hf,
-    Hexagon::V6_vmpy_qf32,        Hexagon::V6_vmpy_qf32_hf,
-    Hexagon::V6_vmpy_qf32_mix_hf, Hexagon::V6_vmpy_qf32_qf16,
-    Hexagon::V6_vmpy_qf32_sf,     Hexagon::V6_vsub_hf,
-    Hexagon::V6_vsub_qf16,        Hexagon::V6_vsub_qf16_mix,
-    Hexagon::V6_vsub_qf32,        Hexagon::V6_vsub_qf32_mix,
-    Hexagon::V6_vsub_sf};
-
+namespace {
 const std::map<unsigned short, unsigned short> QFPInstMap{
     {Hexagon::V6_vadd_hf, Hexagon::V6_vadd_qf16_mix},
     {Hexagon::V6_vadd_qf16_mix, Hexagon::V6_vadd_qf16},
@@ -115,7 +102,7 @@ const std::map<unsigned short, unsigned short> QFPInstMap{
     {Hexagon::V6_vmpy_qf32_hf, Hexagon::V6_vmpy_qf32_mix_hf},
     {Hexagon::V6_vmpy_qf32_mix_hf, Hexagon::V6_vmpy_qf32_qf16},
     {Hexagon::V6_vmpy_qf32_sf, Hexagon::V6_vmpy_qf32}};
-}
+} // namespace
 
 namespace llvm {
 
@@ -130,7 +117,12 @@ struct HexagonQFPoptimizer : public MachineFunctionPass {
 public:
   static char ID;
 
-  HexagonQFPoptimizer() : MachineFunctionPass(ID) {}
+  HexagonQFPoptimizer() : MachineFunctionPass(ID) {
+    for (const auto &entry : QFPInstMap) {
+      QFPInstSet.insert(entry.first);
+      QFPInstSet.insert(entry.second);
+    }
+  }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
@@ -147,6 +139,7 @@ struct HexagonQFPoptimizer : public MachineFunctionPass {
   const HexagonSubtarget *HST = nullptr;
   const HexagonInstrInfo *HII = nullptr;
   const MachineRegisterInfo *MRI = nullptr;
+  std::unordered_set<unsigned short> QFPInstSet;
 };
 
 char HexagonQFPoptimizer::ID = 0;
@@ -161,16 +154,22 @@ FunctionPass *llvm::createHexagonQFPoptimizer() {
 
 bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
                                       MachineBasicBlock *MBB) {
+  
+  // Early exit:
+  // - if instruction is invalid or has too few operands (QFP ops need 2 sources + 1 dest),
+  // - is not part of the QFP instruction set,
+  // - or does not have a transformation mapping.
   if (MI->getNumOperands() < 3)
     return false;
-
-  unsigned Op0F = 0;
-  unsigned Op1F = 0;
+  if (!QFPInstSet.count(MI->getOpcode()))
+    return false;
   auto It = QFPInstMap.find(MI->getOpcode());
   if (It == QFPInstMap.end())
     return false;
   unsigned short InstTy = It->second;
 
+  unsigned Op0F = 0;
+  unsigned Op1F = 0;
   // Get the reaching defs of MI, DefMI1 and DefMI2
   MachineInstr *DefMI1 = nullptr;
   MachineInstr *DefMI2 = nullptr;
@@ -208,15 +207,14 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
        Def2OP == Hexagon::V6_vconv_hf_qf16)) {
 
     // If the reaching defs of DefMI are W register type, we return
-    if ((Inst1 && Inst1->getNumOperands() > 0 &&
-         Inst1->getOperand(0).isReg() &&
-         MRI->getRegClass(Inst1->getOperand(0).getReg()) == &Hexagon::HvxWRRegClass) ||
-        (Inst2 && Inst2->getNumOperands() > 0 &&
-         Inst2->getOperand(0).isReg() &&
-         MRI->getRegClass(Inst2->getOperand(0).getReg()) == &Hexagon::HvxWRRegClass))
+    if ((Inst1 && Inst1->getNumOperands() > 0 && Inst1->getOperand(0).isReg() &&
+         MRI->getRegClass(Inst1->getOperand(0).getReg()) ==
+             &Hexagon::HvxWRRegClass) ||
+        (Inst2 && Inst2->getNumOperands() > 0 && Inst2->getOperand(0).isReg() &&
+         MRI->getRegClass(Inst2->getOperand(0).getReg()) ==
+             &Hexagon::HvxWRRegClass))
       return false;
 
-
     // Analyze the use operands of the conversion to get their KILL status
     MachineOperand &Src1 = DefMI1->getOperand(1);
     MachineOperand &Src2 = DefMI2->getOperand(1);