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[mlir][Vector] Improve support for 0-d vectors in vector dialect lowerings #112913

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Groverkss opened this issue Oct 18, 2024 · 6 comments · May be fixed by #112937
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[mlir][Vector] Improve support for 0-d vectors in vector dialect lowerings #112913

Groverkss opened this issue Oct 18, 2024 · 6 comments · May be fixed by #112937
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good first issue https://github.com/llvm/llvm-project/contribute mlir:vector

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@Groverkss
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Groverkss commented Oct 18, 2024

A number of patterns in vector dialect lowerings predate 0-d vector support and side step from 0-d vectors by converting them to scalars and then broadcasting them. An example patch fixing this: #112907

Some example issues:

I have tested removing these, and the llvm ir generated from llvm.store with 0-d vectors is correct. (Good first issue)

@Groverkss Groverkss added good first issue https://github.com/llvm/llvm-project/contribute mlir:vector labels Oct 18, 2024
@llvmbot
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llvmbot commented Oct 18, 2024

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

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llvmbot commented Oct 18, 2024

@llvm/issue-subscribers-good-first-issue

Author: Kunwar Grover (Groverkss)

A number of patterns in vector dialect lowerings predate 0-d vector support and side step from 0-d vectors by converting them to scalars and then broadcasting them. An example patch fixing this: https://github.com//pull/112907

Some example issues:

@harrisonGPU
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Hi @Groverkss, do you mean a draft like this? #112937, to merge AnyVector and AnyVectorOfAnyRank type constraints?

@Groverkss
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Hi @Groverkss, do you mean a draft like this? #112937, to merge AnyVector and AnyVectorOfAnyRank type constraints?

Probably not. It would involve supporting 0-d vectors natively for most vector dialect operations and then merging them. My understanding is that these two type constraints exist because 0-d vector support wasn't plumbed through properly.

I think an easier, and more useful patch would be to rename them: AnyVector -> AnyNonZeroRankVector, AnyVectorOfAnyRank -> AnyVector . The current naming is very confusing, and this would be a good first step.

The next step would probably involve supporting 0-d vectors in vector.multi_reduction, vector.contract and then other ops.

@harrisonGPU
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Hi @Groverkss, do you mean a draft like this? #112937, to merge AnyVector and AnyVectorOfAnyRank type constraints?

Probably not. It would involve supporting 0-d vectors natively for most vector dialect operations and then merging them. My understanding is that these two type constraints exist because 0-d vector support wasn't plumbed through properly.

I think an easier, and more useful patch would be to rename them: AnyVector -> AnyNonZeroRankVector, AnyVectorOfAnyRank -> AnyVector . The current naming is very confusing, and this would be a good first step.

The next step would probably involve supporting 0-d vectors in vector.multi_reduction, vector.contract and then other ops.

Thanks, I will consiconsider it! :)

@meltq
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meltq commented Jan 2, 2025

Since this issue hasn't gotten much activity in 2 months, I've begun working on it here #121454

hanhanW pushed a commit that referenced this issue Jan 22, 2025
0-d vectors are supported now and so these patterns are no longer
required. This covers a part of this issue
#112913 . Additionally this
removes %arg2 in mlir/test/Conversion/GPUCommon/transfer_write.mlir and
renames %arg3 to %arg2 as %arg2 was originally not required.
github-actions bot pushed a commit to arm/arm-toolchain that referenced this issue Jan 22, 2025
…ng (#121454)

0-d vectors are supported now and so these patterns are no longer
required. This covers a part of this issue
llvm/llvm-project#112913 . Additionally this
removes %arg2 in mlir/test/Conversion/GPUCommon/transfer_write.mlir and
renames %arg3 to %arg2 as %arg2 was originally not required.
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