[RISCV] Verifier failure in the RISCVMoveMerger pass

[svs-quic]

https://godbolt.org/z/jEeEcsMMe

When we run the RISCVMoveMerger pass on the following MIR with -mattr=+zcmp we run into verifier issues on using an undefined register:

---
name: mov-merge
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x8, $x9
    $x12 = ADDI $x0, -3
    SW renamable $x9, $x2, 56
    $x10 = ADDI killed renamable $x9, 0
    SW renamable $x8, $x2, 60
    $x11 = ADDI killed renamable $x8, 0
    PseudoRET
...

The error is:

*** Bad machine code: Using an undefined physical register ***
- function:    mov-merge
- basic block: %bb.0 entry (0x2b403d40)
- instruction: SW renamable $x8, $x2, 60
- operand 0:   renamable $x8
LLVM ERROR: Found 1 machine code errors.

It looks like we always insert the merged move after the first MV instruction thereby missing cases where the source register in the second MV is killed in between.

[svs-quic]

Checking for Uses of the source reg of the second instruction and conservatively inserting the merged move after it seems to solve the issue but I'm not sure if there are cases where this might cause similar verifier issues with the first instruction.

diff --git a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
index 7a2541a652b5..83bb093e7d0d 100644
--- a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
@@ -135,7 +135,6 @@ RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,

   if (NextI == Paired)
     NextI = next_nodbg(NextI, E);
-  DebugLoc DL = I->getDebugLoc();

   // The order of S-reg depends on which instruction holds A0, instead of
   // the order of register pair.
@@ -154,7 +153,10 @@ RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,
     Sreg2 = StartWithX10 ? PairedRegs.Destination : FirstPair.Destination;
   }

-  BuildMI(*I->getParent(), I, DL, TII->get(Opcode)).add(*Sreg1).add(*Sreg2);
+  if (!UsedRegUnits.available(PairedRegs.Source->getReg()))
+    BuildMI(*Paired->getParent(), Paired, Paired->getDebugLoc(), TII->get(Opcode)).add(*Sreg1).add(*Sreg2);
+  else
+    BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(Opcode)).add(*Sreg1).add(*Sreg2);

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

https://godbolt.org/z/jEeEcsMMe

When we run the RISCVMoveMerger pass on the following MIR with -mattr=+zcmp we run into verifier issues on using an undefined register:

---
name: mov-merge
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x8, $x9
    $x12 = ADDI $x0, -3
    SW renamable $x9, $x2, 56
    $x10 = ADDI killed renamable $x9, 0
    SW renamable $x8, $x2, 60
    $x11 = ADDI killed renamable $x8, 0
    PseudoRET
...

The error is:

*** Bad machine code: Using an undefined physical register ***
- function:    mov-merge
- basic block: %bb.0 entry (0x2b403d40)
- instruction: SW renamable $x8, $x2, 60
- operand 0:   renamable $x8
LLVM ERROR: Found 1 machine code errors.

It looks like we always insert the merged move after the first MV instruction thereby missing cases where the source register in the second MV is killed in between.

[topperc]

/cherry-pick defbbf0

[llvmbot]

/pull-request #153697