Segmentation fault in MIPS64-gnuabi64 SelectionDAG #63608
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Noratrieb
changed the title
EugeneZelenko
added
backend:MIPS
crash
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@llvm/issue-subscribers-backend-mips |
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LLVM version 15.0.7 can reproduce this behavior😢 |
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llc 14.0.0 appears to reject this IR unless you pass llc 13.0.0 seems to complete isel with the following output in Godbolt: uwu: # @uwu
daddiu $1, $zero, 1
dsll $1, $1, 32
daddiu $1, $1, -1
dsll $2, $6, 32
daddiu $3, $zero, 8
sdl $2, 0($3)
and $1, $5, $1
dsll $3, $4, 32
or $1, $1, $3
sdl $1, 0($zero)
daddiu $3, $zero, 15
sdr $2, 0($3)
daddiu $2, $zero, 7
jr $ra
sdr $1, 0($2) |
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It appears to break when the vector is oddly sized, except for 1 x i32 which just returns a 0. |
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Hits a debug assertion: https://llvm.godbolt.org/z/ebPz7WP9e |
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The vector is passed on three i64 registers. getCopyFromPartsVector() will produce a BUILD_VECTOR to v3i64 and then tries to convert that into v5i32. In this case one would need to BITCAST that to v6i32 first, before performing the EXTRACT_SUBVECTOR to v5i32. The current code doesn't support this. |
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I believe https://gist.github.com/nikic/fe10841e5e82f30421f2fc9358875025 should fix the argument lowering side of this, but the same issue also needs to be fixed for call lowering in getCopyToPartsVector(). |
It's simple to add typed pointers: ; ModuleID = 'reduced.bc'
target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
target triple = "mips64-unknown-linux-gnuabi64"
define internal fastcc void @uwu(<5 x i32> %self.8.val) {
start:
store <5 x i32> %self.8.val, <5 x i32>* null, align 4
ret void
}That still crashes with llc-14, but it's ok with llc-13, with the same godbolt output as before. |
I built the LLVM git against the patch you have published. It no longer crashes, the resulting assembly is shown below: Output of
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This patch handles the original case on both the call and argument side: https://gist.github.com/nikic/a52f764ee0ba211ddfd98a50e3df009d However, this breaks down when combined with illegal integer types. For example, mips is trying to pass This makes me wonder whether it wouldn't be better to change the used ABI here, at least for non-power-of-two types and element counts. |
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I ended up going with the second option. Candidate patch: https://reviews.llvm.org/D154445 |
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Any news? Old embedded devices take up a lot of space, such as home routers. |
This issue has been fixed a year ago. If you still see a related problem, please file a new issue. |
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The Mips MSA ABI requires that legal vector types are passed in scalar registers in packed representation. E.g. a type like v16i8 would be passed as two i64 registers. The implementation attempts to do the same for illegal vectors with non-power-of-two element counts or non-power-of-two element types. However, the SDAG argument lowering code doesn't support this, and it is not easy to extend it to support this (we would have to deal with situations like passing v7i18 as two i64 values). This patch instead opts to restrict the special argument lowering to only vectors with power-of-two elements and round element types. Everything else is lowered naively, that is by passing each element in promoted registers. Fixes llvm/llvm-project#63608. Differential Revision: https://reviews.llvm.org/D154445
This been causing lots of spurious failures in Rust's CI recently, see rust-lang/rust#113065
llc code.llthe issue was originally discovered and reproduced on x86-64 Ubuntu 20 on LLVM 22897bc, I've done the reduction on NixOS using its
llvmPackages_16package.The text was updated successfully, but these errors were encountered: