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Missing memoperands prevents ARM load/store folding in a few cases #7901
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I've looked into this. The main issue is when the register allocator folded reloads from fixed slots the loads ended up with alignment 1. That's because by default all fixed slots have alignment of 1. This is overly conservative. DAG combiner will infer the correct alignments from stack pointer alignments and frame offset. But at register allocation time we are simply taking the frame object's alignments. I think the right fix is to make sure the fixed objects have the inferred alignments when they are created. Does anyone see a problem with that? |
Fixed: 107591. Jakob, please verify. |
I think your patch in 107591 is definitely correct, and it should provide more ldm/stm folding, but the original 107114 only changed the behavior for loads and stores without any memoperands. 107591 doesn't add memoperands to to loads and stores that don't have any, right? |
Right. I think that's the right behavior. I looked a few changes due to 107114. They all look like they are related to remat of loads from fixed slots. Are there other missing cases? |
I think that is al |
…as-driver-cache-launcher-test-fix [clang][CAS] Fix the "CAS/driver-cache-launcher.c" test
Extended Description
Revision 107114 changed the ARMLoadStoreOptimizer pass to not touch loads and stores with missing memoperands. When there is no memoperand to say otherwise, the memory access could be unaligned or volatile.
This caused a small change in code generation - 0.2% of ldms and 0.1% of stms lost across the nightly test suite.
We should check why those loads and stores had no memoperands, and if we are missing some possible optimizations.
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