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[LLVM][ISel][SVE] Remove redundant merging fp patterns. #101351

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Merged
merged 1 commit into from
Aug 1, 2024
Merged

[LLVM][ISel][SVE] Remove redundant merging fp patterns. #101351

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12 changes: 0 additions & 12 deletions llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -239,18 +239,6 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
return false;
}

bool SelectDupNegativeZero(SDValue N) {
switch(N->getOpcode()) {
case AArch64ISD::DUP:
case ISD::SPLAT_VECTOR: {
ConstantFPSDNode *Const = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
return Const && Const->isZero() && Const->isNegative();
}
}

return false;
}

template<MVT::SimpleValueType VT>
bool SelectSVEAddSubImm(SDValue N, SDValue &Imm, SDValue &Shift) {
return SelectSVEAddSubImm(N, VT, Imm, Shift);
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16 changes: 2 additions & 14 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -213,18 +213,10 @@ def AArch64fadd_p_contract : PatFrag<(ops node:$op1, node:$op2, node:$op3),
(AArch64fadd_p node:$op1, node:$op2, node:$op3), [{
return N->getFlags().hasAllowContract();
}]>;
def AArch64fadd_p_nsz : PatFrag<(ops node:$op1, node:$op2, node:$op3),
(AArch64fadd_p node:$op1, node:$op2, node:$op3), [{
return N->getFlags().hasNoSignedZeros();
}]>;
def AArch64fsub_p_contract : PatFrag<(ops node:$op1, node:$op2, node:$op3),
(AArch64fsub_p node:$op1, node:$op2, node:$op3), [{
return N->getFlags().hasAllowContract();
}]>;
def AArch64fsub_p_nsz : PatFrag<(ops node:$op1, node:$op2, node:$op3),
(AArch64fsub_p node:$op1, node:$op2, node:$op3), [{
return N->getFlags().hasNoSignedZeros();
}]>;

def SDT_AArch64Arith_Imm : SDTypeProfile<1, 3, [
SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVT<3,i32>,
Expand Down Expand Up @@ -281,15 +273,11 @@ def AArch64not_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_
def AArch64fmul_m1 : VSelectPredOrPassthruPatFrags<int_aarch64_sve_fmul, AArch64fmul_p>;
def AArch64fadd_m1 : PatFrags<(ops node:$pg, node:$op1, node:$op2), [
(int_aarch64_sve_fadd node:$pg, node:$op1, node:$op2),
(vselect node:$pg, (AArch64fadd_p (SVEAllActive), node:$op1, node:$op2), node:$op1),
(AArch64fadd_p_nsz (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDup0))),
(AArch64fadd_p (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDupNeg0)))
(vselect node:$pg, (AArch64fadd_p (SVEAllActive), node:$op1, node:$op2), node:$op1)
]>;
def AArch64fsub_m1 : PatFrags<(ops node:$pg, node:$op1, node:$op2), [
(int_aarch64_sve_fsub node:$pg, node:$op1, node:$op2),
(vselect node:$pg, (AArch64fsub_p (SVEAllActive), node:$op1, node:$op2), node:$op1),
(AArch64fsub_p (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDup0))),
(AArch64fsub_p_nsz (SVEAllActive), node:$op1, (vselect node:$pg, node:$op2, (SVEDupNeg0)))
(vselect node:$pg, (AArch64fsub_p (SVEAllActive), node:$op1, node:$op2), node:$op1)
]>;

def AArch64shadd : PatFrags<(ops node:$pg, node:$op1, node:$op2),
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1 change: 0 additions & 1 deletion llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -446,7 +446,6 @@ multiclass SVE_1_Op_PassthruUndef_Round_Pat<ValueType vtd, SDPatternOperator op,
}

def SVEDup0 : ComplexPattern<vAny, 0, "SelectDupZero", []>;
def SVEDupNeg0 : ComplexPattern<vAny, 0, "SelectDupNegativeZero", []>;

class SVE_1_Op_PassthruZero_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
ValueType vt2, Instruction inst>
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