[MC] Update MCOperand::getReg/setReg/createReg and MCInstBuilder::addReg to use MCRegister. #106015
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…Reg to use MCRegister. Replace unsigned with MCRegister. Update some ternary operators that started giving errors.
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@llvm/pr-subscribers-backend-loongarch @llvm/pr-subscribers-backend-amdgpu Author: Craig Topper (topperc) ChangesReplace unsigned with MCRegister. Update some ternary operators that started giving errors. Full diff: https://github.com/llvm/llvm-project/pull/106015.diff 7 Files Affected:
diff --git a/llvm/include/llvm/MC/MCInst.h b/llvm/include/llvm/MC/MCInst.h
index 578b7328970b76..b3d615b4392f55 100644
--- a/llvm/include/llvm/MC/MCInst.h
+++ b/llvm/include/llvm/MC/MCInst.h
@@ -18,6 +18,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/bit.h"
+#include "llvm/MC/MCRegister.h"
#include "llvm/Support/SMLoc.h"
#include <cassert>
#include <cstddef>
@@ -66,15 +67,15 @@ class MCOperand {
bool isInst() const { return Kind == kInst; }
/// Returns the register number.
- unsigned getReg() const {
+ MCRegister getReg() const {
assert(isReg() && "This is not a register operand!");
return RegVal;
}
/// Set the register number.
- void setReg(unsigned Reg) {
+ void setReg(MCRegister Reg) {
assert(isReg() && "This is not a register operand!");
- RegVal = Reg;
+ RegVal = Reg.id();
}
int64_t getImm() const {
@@ -131,10 +132,10 @@ class MCOperand {
InstVal = Val;
}
- static MCOperand createReg(unsigned Reg) {
+ static MCOperand createReg(MCRegister Reg) {
MCOperand Op;
Op.Kind = kRegister;
- Op.RegVal = Reg;
+ Op.RegVal = Reg.id();
return Op;
}
diff --git a/llvm/include/llvm/MC/MCInstBuilder.h b/llvm/include/llvm/MC/MCInstBuilder.h
index d06ed4c6c840a9..de45ffb4b2dc7c 100644
--- a/llvm/include/llvm/MC/MCInstBuilder.h
+++ b/llvm/include/llvm/MC/MCInstBuilder.h
@@ -34,7 +34,7 @@ class MCInstBuilder {
}
/// Add a new register operand.
- MCInstBuilder &addReg(unsigned Reg) {
+ MCInstBuilder &addReg(MCRegister Reg) {
Inst.addOperand(MCOperand::createReg(Reg));
return *this;
}
diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp
index 32b20d758ee70b..c4d88856abdfb9 100644
--- a/llvm/lib/MCA/InstrBuilder.cpp
+++ b/llvm/lib/MCA/InstrBuilder.cpp
@@ -799,7 +799,7 @@ InstrBuilder::createInstruction(const MCInst &MCI,
unsigned WriteIndex = 0;
Idx = 0U;
for (const WriteDescriptor &WD : D.Writes) {
- RegID = WD.isImplicitWrite() ? WD.RegisterID
+ RegID = WD.isImplicitWrite() ? MCRegister(WD.RegisterID)
: MCI.getOperand(WD.OpIndex).getReg();
// Check if this is a optional definition that references NoReg or a write
// to a constant register.
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 1a10206eea2374..3914f36338fa50 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -3815,7 +3815,7 @@ bool AMDGPUAsmParser::validateVOPDRegBankConstraints(
const MCOperand &Opr = Inst.getOperand(OperandIdx);
return (Opr.isReg() && !isSGPR(mc2PseudoReg(Opr.getReg()), TRI))
? Opr.getReg()
- : MCRegister::NoRegister;
+ : MCRegister();
};
// On GFX12 if both OpX and OpY are V_MOV_B32 then OPY uses SRC2 source-cache.
@@ -4753,7 +4753,7 @@ static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,
if (!Op.isReg())
return -1;
- unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
+ MCRegister Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
auto Reg = Sub ? Sub : Op.getReg();
const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
return AGPR32.contains(Reg) ? 1 : 0;
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 1a0dc7098347ac..b1da9da19c69b1 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -382,7 +382,7 @@ static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
if (!Op.isReg())
return false;
- unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
+ MCRegister Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
auto Reg = Sub ? Sub : Op.getReg();
return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
}
diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
index f52e188f877920..c2ae4a0734b6a7 100644
--- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
@@ -1314,8 +1314,8 @@ void LoongArchAsmParser::emitFuncCall36(MCInst &Inst, SMLoc IDLoc,
// expands to:
// pcaddu18i $rj, %call36(sym)
// jirl $r0, $rj, 0
- unsigned ScratchReg =
- IsTailCall ? Inst.getOperand(0).getReg() : (unsigned)LoongArch::R1;
+ MCRegister ScratchReg =
+ IsTailCall ? Inst.getOperand(0).getReg() : MCRegister(LoongArch::R1);
const MCExpr *Sym =
IsTailCall ? Inst.getOperand(1).getExpr() : Inst.getOperand(0).getExpr();
const LoongArchMCExpr *LE = LoongArchMCExpr::create(
@@ -1326,7 +1326,7 @@ void LoongArchAsmParser::emitFuncCall36(MCInst &Inst, SMLoc IDLoc,
getSTI());
Out.emitInstruction(
MCInstBuilder(LoongArch::JIRL)
- .addReg(IsTailCall ? (unsigned)LoongArch::R0 : ScratchReg)
+ .addReg(IsTailCall ? MCRegister(LoongArch::R0) : ScratchReg)
.addReg(ScratchReg)
.addImm(0),
getSTI());
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 076e0a20cb97e9..c50c2063ee8edf 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -5782,9 +5782,9 @@ bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
sel = 3;
break;
}
- unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;
- unsigned Op1 =
- IsMFTR ? rd
+ MCRegister Op0 = IsMFTR ? Inst.getOperand(0).getReg() : MCRegister(rd);
+ MCRegister Op1 =
+ IsMFTR ? MCRegister(rd)
: (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
: Inst.getOperand(0).getReg());
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Replace unsigned with MCRegister.
Update some ternary operators that started giving errors.