[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 #114293

SpencerAbson · 2024-10-30T18:43:46Z

This patch introduces the amended feature flag for FEAT_SVE_AES, 'sve-aes'. The existing flag associated with this feature, 'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for backwards compatibility.

The ACLE documents __ARM_FEATURE_SVE2_AES, which was previously defined to 1 when

there is hardware support for the SVE2 AES (FEAT_SVE_AES) instructions and if the associated ACLE intrinsics are available.

The front-end has been amended such that it is compatible with +sve2-aes and +sve2+sve-aes.

- Introduce the ammended feature flag for FEAT_SVE_AES, 'sve-aes' - Make the existing sve2-aes flag as an alias of +sve2+sve-aes - The exising __ARM_FEATURE_SVE2_AES macro must not be effected by this change, so an effort has been made to ensure it is defined when we have supplied target features +sve-aes and +sve2 by any method.

llvmbot · 2024-10-30T18:44:19Z

@llvm/pr-subscribers-lldb
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-clang

Author: None (SpencerAbson)

Changes

This patch introduces the amended feature flag for FEAT_SVE_AES, 'sve-aes'. The existing flag associated with this feature, 'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for backwards compatibility.

The ACLE documents __ARM_FEATURE_SVE2_AES, which was previously defined to 1 when +sve2-aes was supplied. The front-end has been amended such that it is compatible with +sve2-aes and +sve2+sve-aes.

Full diff: https://github.com/llvm/llvm-project/pull/114293.diff

8 Files Affected:

(modified) clang/lib/Basic/Targets/AArch64.cpp (+8-3)
(modified) clang/lib/Basic/Targets/AArch64.h (+1-1)
(modified) clang/test/Driver/aarch64-implied-sve-features.c (+7-4)
(modified) clang/test/Driver/print-supported-extensions-aarch64.c (+3-2)
(modified) clang/test/Preprocessor/aarch64-target-features.c (+12)
(modified) llvm/lib/Target/AArch64/AArch64Features.td (+6-3)
(modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+1)
(modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+23-6)

diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 3d8de0294d4ba3..6033a0439a99af 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -473,7 +473,7 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasSVE2p1)
     Builder.defineMacro("__ARM_FEATURE_SVE2p1", "1");
 
-  if (HasSVE2 && HasSVE2AES)
+  if (HasSVE2 && HasSVEAES)
     Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
 
   if (HasSVE2 && HasSVE2BitPerm)
@@ -769,7 +769,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
       .Case("f32mm", FPU & SveMode && HasMatmulFP32)
       .Case("f64mm", FPU & SveMode && HasMatmulFP64)
       .Case("sve2", FPU & SveMode && HasSVE2)
-      .Case("sve2-pmull128", FPU & SveMode && HasSVE2AES)
+      .Case("sve2-pmull128", FPU & SveMode && HasSVEAES && HasSVE2)
       .Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm)
       .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
       .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
@@ -861,12 +861,17 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       HasSVE2 = true;
       HasSVE2p1 = true;
     }
+    if (Feature == "+sve-aes") {
+      FPU |= NeonMode;
+      HasAES = true;
+      HasSVEAES = true;
+    }
     if (Feature == "+sve2-aes") {
       FPU |= NeonMode;
       FPU |= SveMode;
       HasFullFP16 = true;
       HasSVE2 = true;
-      HasSVE2AES = true;
+      HasSVEAES = true;
     }
     if (Feature == "+sve2-sha3") {
       FPU |= NeonMode;
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index ea3e4015d84265..4c25bdb5bb16df 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -78,7 +78,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
   bool HasBFloat16 = false;
   bool HasSVE2 = false;
   bool HasSVE2p1 = false;
-  bool HasSVE2AES = false;
+  bool HasSVEAES = false;
   bool HasSVE2SHA3 = false;
   bool HasSVE2SM4 = false;
   bool HasSVEB16B16 = false;
diff --git a/clang/test/Driver/aarch64-implied-sve-features.c b/clang/test/Driver/aarch64-implied-sve-features.c
index f04e1a785673b8..5da138a70a8fbf 100644
--- a/clang/test/Driver/aarch64-implied-sve-features.c
+++ b/clang/test/Driver/aarch64-implied-sve-features.c
@@ -36,7 +36,7 @@
 // SVE2-BITPERM-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-bitperm"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES-REVERT
-// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-aes"
+// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "+sve-aes" "-target-feature" "+sve2" "-target-feature" "-sve2-aes"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3+nosve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3-REVERT
 // SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3"
@@ -47,8 +47,11 @@
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3
 // SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3"
 
+// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-AES
+// SVE-AES: "-target-feature" "+aes"{{.*}} "-target-feature" "+sve-aes"
+
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES
-// SVE2-AES: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
+// SVE2-AES: "-target-feature" "+sve" "-target-feature" "+sve-aes" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4
 // SVE2-SM4: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sm4"
@@ -65,8 +68,8 @@
 // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve2"
 // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve"
 
-// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve+sve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT-REV
-// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
+// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve+sve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT-REV
+// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-bitperm"
 
 // RUN: %clang --target=aarch64-linux-gnu -mcpu=neoverse-n2+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE-MCPU-FEATURES
 // SVE-MCPU-FEATURES-NOT: "-target-feature" "+sve2-bitperm"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 03eacf99736f9e..205c717d8967cf 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -77,17 +77,18 @@
 // CHECK-NEXT:     profile             FEAT_SPE                                               Enable Statistical Profiling extension
 // CHECK-NEXT:     predres2            FEAT_SPECRES2                                          Enable Speculation Restriction Instruction
 // CHECK-NEXT:     ssbs                FEAT_SSBS, FEAT_SSBS2                                  Enable Speculative Store Bypass Safe bit
-// CHECK-NEXT:     ssve-aes            FEAT_SSVE_AES                                          Enable Armv9.6-A SVE2 AES support in streaming SVE mode
+// CHECK-NEXT:     ssve-aes            FEAT_SSVE_AES                                          Enable Armv9.6-A SVE AES support in streaming SVE mode
 // CHECK-NEXT:     ssve-fp8dot2        FEAT_SSVE_FP8DOT2                                      Enable SVE2 FP8 2-way dot product instructions
 // CHECK-NEXT:     ssve-fp8dot4        FEAT_SSVE_FP8DOT4                                      Enable SVE2 FP8 4-way dot product instructions
 // CHECK-NEXT:     ssve-fp8fma         FEAT_SSVE_FP8FMA                                       Enable SVE2 FP8 multiply-add instructions
 // CHECK-NEXT:     sve                 FEAT_SVE                                               Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT:     sve-aes             FEAT_SVE_AES, FEAT_SVE_PMULL128                        Enable SVE AES and 128-bit PMULL instructions
 // CHECK-NEXT:     sve-aes2            FEAT_SVE_AES2                                          Enable Armv9.6-A SVE multi-vector AES and 128-bit PMULL instructions
 // CHECK-NEXT:     sve-b16b16          FEAT_SVE_B16B16                                        Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions
 // CHECK-NEXT:     sve-bfscale         FEAT_SVE_BFSCALE                                       Enable Armv9.6-A SVE BFloat16 scaling instructions
 // CHECK-NEXT:     sve-f16f32mm        FEAT_SVE_F16F32MM                                      Enable Armv9.6-A FP16 to FP32 Matrix Multiply
 // CHECK-NEXT:     sve2                FEAT_SVE2                                              Enable Scalable Vector Extension 2 (SVE2) instructions
-// CHECK-NEXT:     sve2-aes            FEAT_SVE_AES, FEAT_SVE_PMULL128                        Enable AES SVE2 instructions
+// CHECK-NEXT:     sve2-aes                                                                   An alias of +sve2+sve-aes
 // CHECK-NEXT:     sve2-bitperm        FEAT_SVE_BitPerm                                       Enable bit permutation SVE2 instructions
 // CHECK-NEXT:     sve2-sha3           FEAT_SVE_SHA3                                          Enable SHA3 SVE2 instructions
 // CHECK-NEXT:     sve2-sm4            FEAT_SVE_SM4                                           Enable SM4 SVE2 instructions
diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c
index 418430b0b19b89..fc786f4b2e9b4d 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -227,8 +227,20 @@
 // CHECK-NONEON-NOT: __ARM_FEATURE_SVE 1
 // CHECK-NONEON-NOT: __ARM_NEON 1
 
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve-aes -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVEAES %s
+// CHECK-SVEAES: __ARM_FEATURE_AES 1
+
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-aes -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2AES %s
+// CHECK-SVE2AES: __ARM_FEATURE_AES 1
+// CHECK-SVE2AES: __ARM_FEATURE_SVE2 1
 // CHECK-SVE2AES: __ARM_FEATURE_SVE2_AES 1
+
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve-aes+sve2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVEAES-SVE2 %s
+// CHECK-SVEAES-SVE2: __ARM_FEATURE_AES 1
+// CHECK-SVEAES-SVE2: __ARM_FEATURE_SVE2 1
+// CHECK-SVEAES-SVE2: __ARM_FEATURE_SVE2_AES 1
+
+
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-sha3 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SHA3 %s
 // CHECK-SVE2SHA3: __ARM_FEATURE_SVE2_SHA3 1
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-sm4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SM4 %s
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index e481da74ba2d6e..7e4473a3844377 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -369,9 +369,12 @@ def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",
   "Enable Scalable Vector Extension 2 (SVE2) instructions",
   [FeatureSVE, FeatureUseScalarIncVL]>;
 
-def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
+def FeatureSVEAES : ExtensionWithMArch<"sve-aes", "SVEAES",
   "FEAT_SVE_AES, FEAT_SVE_PMULL128",
-  "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
+  "Enable SVE AES and 128-bit PMULL instructions", [FeatureAES]>;
+
+def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES", "",
+  "An alias of +sve2+sve-aes", [FeatureSVE2, FeatureSVEAES]>;
 
 def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
   "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
@@ -542,7 +545,7 @@ def FeatureSME2p2: ExtensionWithMArch<"sme2p2", "SME2p2", "FEAT_SME2p2",
   "Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions", [FeatureSME2p1]>;
 
 def FeatureSSVE_AES : ExtensionWithMArch<"ssve-aes", "SSVE_AES", "FEAT_SSVE_AES",
-  "Enable Armv9.6-A SVE2 AES support in streaming SVE mode", [FeatureSME2, FeatureSVE2AES]>;
+  "Enable Armv9.6-A SVE AES support in streaming SVE mode", [FeatureSME2, FeatureSVEAES]>;
 
 def FeatureSVE2p2 : ExtensionWithMArch<"sve2p2", "SVE2p2", "FEAT_SVE2p2",
   "Enable Armv9.6-A Scalable Vector Extension 2.2 instructions", [FeatureSVE2p1]>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 5a487be5723ce9..f1ca5b016a295f 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3734,6 +3734,7 @@ static const struct Extension {
     {"rng", {AArch64::FeatureRandGen}},
     {"sve", {AArch64::FeatureSVE}},
     {"sve-b16b16", {AArch64::FeatureSVEB16B16}},
+    {"sve-aes", {AArch64::FeatureSVEAES}},
     {"sve2", {AArch64::FeatureSVE2}},
     {"sve2-aes", {AArch64::FeatureSVE2AES}},
     {"sve2-sm4", {AArch64::FeatureSVE2SM4}},
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index d69b2d6b13b1a6..ab0bb1d18d32d3 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1334,6 +1334,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
       AArch64::AEK_FPRCVT,       AArch64::AEK_CMPBR,
       AArch64::AEK_LSUI,         AArch64::AEK_OCCMO,
       AArch64::AEK_PCDPHINT,     AArch64::AEK_POPS,
+      AArch64::AEK_SVEAES
   };
 
   std::vector<StringRef> Features;
@@ -1369,6 +1370,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
   EXPECT_TRUE(llvm::is_contained(Features, "+sve-bfscale"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve-f16f32mm"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+sve-aes"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2-aes"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sm4"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sha3"));
@@ -1538,6 +1540,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
       {"sve-bfscale", "nosve-bfscale", "+sve-bfscale", "-sve-bfscale"},
       {"sve-f16f32mm", "nosve-f16f32mm", "+sve-f16f32mm", "-sve-f16f32mm"},
       {"sve2", "nosve2", "+sve2", "-sve2"},
+      {"sve-aes", "nosve-aes", "+sve-aes", "-sve-aes"},
       {"sve2-aes", "nosve2-aes", "+sve2-aes", "-sve2-aes"},
       {"sve2-sm4", "nosve2-sm4", "+sve2-sm4", "-sve2-sm4"},
       {"sve2-sha3", "nosve2-sha3", "+sve2-sha3", "-sve2-sha3"},
@@ -1840,7 +1843,11 @@ AArch64ExtensionDependenciesBaseArchTestParams
          {},
          {"sve", "sve-f16f32mm"}},
 
-        // sve2 -> {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4}
+        // aes -> {sve-aes}
+        {AArch64::ARMV8A, {"noaes", "sve-aes"}, {"aes", "sve-aes"}, {}},
+        {AArch64::ARMV8A, {"sve-aes", "noaes"}, {}, {"aes", "sve-aes"}},
+
+        // sve2 -> {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes}
         {AArch64::ARMV8A, {"nosve2", "sve2p1"}, {"sve2", "sve2p1"}, {}},
         {AArch64::ARMV8A, {"sve2p1", "nosve2"}, {}, {"sve2", "sve2p1"}},
         {AArch64::ARMV8A,
@@ -1855,6 +1862,8 @@ AArch64ExtensionDependenciesBaseArchTestParams
         {AArch64::ARMV8A, {"sve2-sha3", "nosve2"}, {}, {"sve2", "sve2-sha3"}},
         {AArch64::ARMV8A, {"nosve2", "sve2-sm4"}, {"sve2", "sve2-sm4"}, {}},
         {AArch64::ARMV8A, {"sve2-sm4", "nosve2"}, {}, {"sve2", "sve2-sm4"}},
+        {AArch64::ARMV8A, {"nosve2", "sve2-aes"}, {"sve2", "sve2-aes"}, {}},
+        {AArch64::ARMV8A, {"sve2-aes", "nosve2"}, {}, {"sve2", "sve2-aes"}},
 
         // sve-b16b16 -> {sme-b16b16}
         {AArch64::ARMV9_4A,
@@ -1955,15 +1964,23 @@ AArch64ExtensionDependenciesBaseArchTestParams
         {AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}},
         {AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}},
 
-        // sve2-aes -> ssve-aes
+        // sve-aes -> {ssve-aes, sve2-aes}
+        {AArch64::ARMV9_6A,
+         {"nosve-aes", "ssve-aes"},
+         {"sve-aes", "ssve-aes"},
+         {}},
+        {AArch64::ARMV9_6A,
+         {"ssve-aes", "nosve-aes"},
+         {},
+         {"ssve-aes", "sve-aes"}},
         {AArch64::ARMV9_6A,
-         {"nosve2-aes", "ssve-aes"},
-         {"sve2-aes", "ssve-aes"},
+         {"nosve-aes", "sve2-aes"},
+         {"sve2-aes", "sve-aes"},
          {}},
         {AArch64::ARMV9_6A,
-         {"ssve-aes", "nosve2-aes"},
+         {"sve2-aes", "nosve-aes"},
          {},
-         {"ssve-aes", "sve2-aes"}},
+         {"sve2-aes", "sve-aes"}}
 };
 
 INSTANTIATE_TEST_SUITE_P(

llvmbot · 2024-10-30T18:44:20Z

@llvm/pr-subscribers-clang-driver

Author: None (SpencerAbson)

Changes

This patch introduces the amended feature flag for FEAT_SVE_AES, 'sve-aes'. The existing flag associated with this feature, 'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for backwards compatibility.

The ACLE documents __ARM_FEATURE_SVE2_AES, which was previously defined to 1 when +sve2-aes was supplied. The front-end has been amended such that it is compatible with +sve2-aes and +sve2+sve-aes.

Full diff: https://github.com/llvm/llvm-project/pull/114293.diff

8 Files Affected:

(modified) clang/lib/Basic/Targets/AArch64.cpp (+8-3)
(modified) clang/lib/Basic/Targets/AArch64.h (+1-1)
(modified) clang/test/Driver/aarch64-implied-sve-features.c (+7-4)
(modified) clang/test/Driver/print-supported-extensions-aarch64.c (+3-2)
(modified) clang/test/Preprocessor/aarch64-target-features.c (+12)
(modified) llvm/lib/Target/AArch64/AArch64Features.td (+6-3)
(modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+1)
(modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+23-6)

diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 3d8de0294d4ba3..6033a0439a99af 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -473,7 +473,7 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasSVE2p1)
     Builder.defineMacro("__ARM_FEATURE_SVE2p1", "1");
 
-  if (HasSVE2 && HasSVE2AES)
+  if (HasSVE2 && HasSVEAES)
     Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1");
 
   if (HasSVE2 && HasSVE2BitPerm)
@@ -769,7 +769,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
       .Case("f32mm", FPU & SveMode && HasMatmulFP32)
       .Case("f64mm", FPU & SveMode && HasMatmulFP64)
       .Case("sve2", FPU & SveMode && HasSVE2)
-      .Case("sve2-pmull128", FPU & SveMode && HasSVE2AES)
+      .Case("sve2-pmull128", FPU & SveMode && HasSVEAES && HasSVE2)
       .Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm)
       .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
       .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
@@ -861,12 +861,17 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       HasSVE2 = true;
       HasSVE2p1 = true;
     }
+    if (Feature == "+sve-aes") {
+      FPU |= NeonMode;
+      HasAES = true;
+      HasSVEAES = true;
+    }
     if (Feature == "+sve2-aes") {
       FPU |= NeonMode;
       FPU |= SveMode;
       HasFullFP16 = true;
       HasSVE2 = true;
-      HasSVE2AES = true;
+      HasSVEAES = true;
     }
     if (Feature == "+sve2-sha3") {
       FPU |= NeonMode;
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index ea3e4015d84265..4c25bdb5bb16df 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -78,7 +78,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
   bool HasBFloat16 = false;
   bool HasSVE2 = false;
   bool HasSVE2p1 = false;
-  bool HasSVE2AES = false;
+  bool HasSVEAES = false;
   bool HasSVE2SHA3 = false;
   bool HasSVE2SM4 = false;
   bool HasSVEB16B16 = false;
diff --git a/clang/test/Driver/aarch64-implied-sve-features.c b/clang/test/Driver/aarch64-implied-sve-features.c
index f04e1a785673b8..5da138a70a8fbf 100644
--- a/clang/test/Driver/aarch64-implied-sve-features.c
+++ b/clang/test/Driver/aarch64-implied-sve-features.c
@@ -36,7 +36,7 @@
 // SVE2-BITPERM-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-bitperm"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES-REVERT
-// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-aes"
+// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "+sve-aes" "-target-feature" "+sve2" "-target-feature" "-sve2-aes"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3+nosve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3-REVERT
 // SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3"
@@ -47,8 +47,11 @@
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3
 // SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3"
 
+// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-AES
+// SVE-AES: "-target-feature" "+aes"{{.*}} "-target-feature" "+sve-aes"
+
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES
-// SVE2-AES: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
+// SVE2-AES: "-target-feature" "+sve" "-target-feature" "+sve-aes" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4
 // SVE2-SM4: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sm4"
@@ -65,8 +68,8 @@
 // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve2"
 // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve"
 
-// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve+sve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT-REV
-// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-aes"
+// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve+sve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT-REV
+// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-bitperm"
 
 // RUN: %clang --target=aarch64-linux-gnu -mcpu=neoverse-n2+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE-MCPU-FEATURES
 // SVE-MCPU-FEATURES-NOT: "-target-feature" "+sve2-bitperm"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 03eacf99736f9e..205c717d8967cf 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -77,17 +77,18 @@
 // CHECK-NEXT:     profile             FEAT_SPE                                               Enable Statistical Profiling extension
 // CHECK-NEXT:     predres2            FEAT_SPECRES2                                          Enable Speculation Restriction Instruction
 // CHECK-NEXT:     ssbs                FEAT_SSBS, FEAT_SSBS2                                  Enable Speculative Store Bypass Safe bit
-// CHECK-NEXT:     ssve-aes            FEAT_SSVE_AES                                          Enable Armv9.6-A SVE2 AES support in streaming SVE mode
+// CHECK-NEXT:     ssve-aes            FEAT_SSVE_AES                                          Enable Armv9.6-A SVE AES support in streaming SVE mode
 // CHECK-NEXT:     ssve-fp8dot2        FEAT_SSVE_FP8DOT2                                      Enable SVE2 FP8 2-way dot product instructions
 // CHECK-NEXT:     ssve-fp8dot4        FEAT_SSVE_FP8DOT4                                      Enable SVE2 FP8 4-way dot product instructions
 // CHECK-NEXT:     ssve-fp8fma         FEAT_SSVE_FP8FMA                                       Enable SVE2 FP8 multiply-add instructions
 // CHECK-NEXT:     sve                 FEAT_SVE                                               Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT:     sve-aes             FEAT_SVE_AES, FEAT_SVE_PMULL128                        Enable SVE AES and 128-bit PMULL instructions
 // CHECK-NEXT:     sve-aes2            FEAT_SVE_AES2                                          Enable Armv9.6-A SVE multi-vector AES and 128-bit PMULL instructions
 // CHECK-NEXT:     sve-b16b16          FEAT_SVE_B16B16                                        Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions
 // CHECK-NEXT:     sve-bfscale         FEAT_SVE_BFSCALE                                       Enable Armv9.6-A SVE BFloat16 scaling instructions
 // CHECK-NEXT:     sve-f16f32mm        FEAT_SVE_F16F32MM                                      Enable Armv9.6-A FP16 to FP32 Matrix Multiply
 // CHECK-NEXT:     sve2                FEAT_SVE2                                              Enable Scalable Vector Extension 2 (SVE2) instructions
-// CHECK-NEXT:     sve2-aes            FEAT_SVE_AES, FEAT_SVE_PMULL128                        Enable AES SVE2 instructions
+// CHECK-NEXT:     sve2-aes                                                                   An alias of +sve2+sve-aes
 // CHECK-NEXT:     sve2-bitperm        FEAT_SVE_BitPerm                                       Enable bit permutation SVE2 instructions
 // CHECK-NEXT:     sve2-sha3           FEAT_SVE_SHA3                                          Enable SHA3 SVE2 instructions
 // CHECK-NEXT:     sve2-sm4            FEAT_SVE_SM4                                           Enable SM4 SVE2 instructions
diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c
index 418430b0b19b89..fc786f4b2e9b4d 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -227,8 +227,20 @@
 // CHECK-NONEON-NOT: __ARM_FEATURE_SVE 1
 // CHECK-NONEON-NOT: __ARM_NEON 1
 
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve-aes -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVEAES %s
+// CHECK-SVEAES: __ARM_FEATURE_AES 1
+
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-aes -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2AES %s
+// CHECK-SVE2AES: __ARM_FEATURE_AES 1
+// CHECK-SVE2AES: __ARM_FEATURE_SVE2 1
 // CHECK-SVE2AES: __ARM_FEATURE_SVE2_AES 1
+
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve-aes+sve2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVEAES-SVE2 %s
+// CHECK-SVEAES-SVE2: __ARM_FEATURE_AES 1
+// CHECK-SVEAES-SVE2: __ARM_FEATURE_SVE2 1
+// CHECK-SVEAES-SVE2: __ARM_FEATURE_SVE2_AES 1
+
+
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-sha3 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SHA3 %s
 // CHECK-SVE2SHA3: __ARM_FEATURE_SVE2_SHA3 1
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-sm4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SM4 %s
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index e481da74ba2d6e..7e4473a3844377 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -369,9 +369,12 @@ def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",
   "Enable Scalable Vector Extension 2 (SVE2) instructions",
   [FeatureSVE, FeatureUseScalarIncVL]>;
 
-def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
+def FeatureSVEAES : ExtensionWithMArch<"sve-aes", "SVEAES",
   "FEAT_SVE_AES, FEAT_SVE_PMULL128",
-  "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
+  "Enable SVE AES and 128-bit PMULL instructions", [FeatureAES]>;
+
+def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES", "",
+  "An alias of +sve2+sve-aes", [FeatureSVE2, FeatureSVEAES]>;
 
 def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
   "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
@@ -542,7 +545,7 @@ def FeatureSME2p2: ExtensionWithMArch<"sme2p2", "SME2p2", "FEAT_SME2p2",
   "Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions", [FeatureSME2p1]>;
 
 def FeatureSSVE_AES : ExtensionWithMArch<"ssve-aes", "SSVE_AES", "FEAT_SSVE_AES",
-  "Enable Armv9.6-A SVE2 AES support in streaming SVE mode", [FeatureSME2, FeatureSVE2AES]>;
+  "Enable Armv9.6-A SVE AES support in streaming SVE mode", [FeatureSME2, FeatureSVEAES]>;
 
 def FeatureSVE2p2 : ExtensionWithMArch<"sve2p2", "SVE2p2", "FEAT_SVE2p2",
   "Enable Armv9.6-A Scalable Vector Extension 2.2 instructions", [FeatureSVE2p1]>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 5a487be5723ce9..f1ca5b016a295f 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3734,6 +3734,7 @@ static const struct Extension {
     {"rng", {AArch64::FeatureRandGen}},
     {"sve", {AArch64::FeatureSVE}},
     {"sve-b16b16", {AArch64::FeatureSVEB16B16}},
+    {"sve-aes", {AArch64::FeatureSVEAES}},
     {"sve2", {AArch64::FeatureSVE2}},
     {"sve2-aes", {AArch64::FeatureSVE2AES}},
     {"sve2-sm4", {AArch64::FeatureSVE2SM4}},
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index d69b2d6b13b1a6..ab0bb1d18d32d3 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1334,6 +1334,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
       AArch64::AEK_FPRCVT,       AArch64::AEK_CMPBR,
       AArch64::AEK_LSUI,         AArch64::AEK_OCCMO,
       AArch64::AEK_PCDPHINT,     AArch64::AEK_POPS,
+      AArch64::AEK_SVEAES
   };
 
   std::vector<StringRef> Features;
@@ -1369,6 +1370,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
   EXPECT_TRUE(llvm::is_contained(Features, "+sve-bfscale"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve-f16f32mm"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+sve-aes"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2-aes"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sm4"));
   EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sha3"));
@@ -1538,6 +1540,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
       {"sve-bfscale", "nosve-bfscale", "+sve-bfscale", "-sve-bfscale"},
       {"sve-f16f32mm", "nosve-f16f32mm", "+sve-f16f32mm", "-sve-f16f32mm"},
       {"sve2", "nosve2", "+sve2", "-sve2"},
+      {"sve-aes", "nosve-aes", "+sve-aes", "-sve-aes"},
       {"sve2-aes", "nosve2-aes", "+sve2-aes", "-sve2-aes"},
       {"sve2-sm4", "nosve2-sm4", "+sve2-sm4", "-sve2-sm4"},
       {"sve2-sha3", "nosve2-sha3", "+sve2-sha3", "-sve2-sha3"},
@@ -1840,7 +1843,11 @@ AArch64ExtensionDependenciesBaseArchTestParams
          {},
          {"sve", "sve-f16f32mm"}},
 
-        // sve2 -> {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4}
+        // aes -> {sve-aes}
+        {AArch64::ARMV8A, {"noaes", "sve-aes"}, {"aes", "sve-aes"}, {}},
+        {AArch64::ARMV8A, {"sve-aes", "noaes"}, {}, {"aes", "sve-aes"}},
+
+        // sve2 -> {sve2p1, sve2-bitperm, sve2-sha3, sve2-sm4, sve2-aes}
         {AArch64::ARMV8A, {"nosve2", "sve2p1"}, {"sve2", "sve2p1"}, {}},
         {AArch64::ARMV8A, {"sve2p1", "nosve2"}, {}, {"sve2", "sve2p1"}},
         {AArch64::ARMV8A,
@@ -1855,6 +1862,8 @@ AArch64ExtensionDependenciesBaseArchTestParams
         {AArch64::ARMV8A, {"sve2-sha3", "nosve2"}, {}, {"sve2", "sve2-sha3"}},
         {AArch64::ARMV8A, {"nosve2", "sve2-sm4"}, {"sve2", "sve2-sm4"}, {}},
         {AArch64::ARMV8A, {"sve2-sm4", "nosve2"}, {}, {"sve2", "sve2-sm4"}},
+        {AArch64::ARMV8A, {"nosve2", "sve2-aes"}, {"sve2", "sve2-aes"}, {}},
+        {AArch64::ARMV8A, {"sve2-aes", "nosve2"}, {}, {"sve2", "sve2-aes"}},
 
         // sve-b16b16 -> {sme-b16b16}
         {AArch64::ARMV9_4A,
@@ -1955,15 +1964,23 @@ AArch64ExtensionDependenciesBaseArchTestParams
         {AArch64::ARMV8A, {"norcpc", "rcpc3"}, {"rcpc", "rcpc3"}, {}},
         {AArch64::ARMV8A, {"rcpc3", "norcpc"}, {}, {"rcpc", "rcpc3"}},
 
-        // sve2-aes -> ssve-aes
+        // sve-aes -> {ssve-aes, sve2-aes}
+        {AArch64::ARMV9_6A,
+         {"nosve-aes", "ssve-aes"},
+         {"sve-aes", "ssve-aes"},
+         {}},
+        {AArch64::ARMV9_6A,
+         {"ssve-aes", "nosve-aes"},
+         {},
+         {"ssve-aes", "sve-aes"}},
         {AArch64::ARMV9_6A,
-         {"nosve2-aes", "ssve-aes"},
-         {"sve2-aes", "ssve-aes"},
+         {"nosve-aes", "sve2-aes"},
+         {"sve2-aes", "sve-aes"},
          {}},
         {AArch64::ARMV9_6A,
-         {"ssve-aes", "nosve2-aes"},
+         {"sve2-aes", "nosve-aes"},
          {},
-         {"ssve-aes", "sve2-aes"}},
+         {"sve2-aes", "sve-aes"}}
 };
 
 INSTANTIATE_TEST_SUITE_P(

github-actions · 2024-10-30T18:47:13Z

✅ With the latest revision this PR passed the C/C++ code formatter.

llvm/lib/Target/AArch64/AArch64Features.td

clang/test/Driver/aarch64-implied-sve-features.c

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

llvm/lib/Target/AArch64/AArch64Features.td

labrinea · 2024-11-08T18:49:44Z

This doesn't seem right. It breaks #113281. I can see your commit ec6f646 which introduced this change. Please add me on the review when making changes to FMV.

labrinea · 2024-11-08T19:32:18Z

llvm/lib/Target/AArch64/AArch64FMV.td

@@ -78,7 +78,7 @@ def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
 def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>;
 def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
 def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
-def : FMVExtension<"sve2-aes", "FEAT_SVE_PMULL128", "+sve2,+sve,+aes,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
+def : FMVExtension<"sve2-aes", "FEAT_SVE_PMULL128", "+sve2,+sve,+aes,+sve-aes,+fullfp16,+fp-armv8,+neon", 380>;


This should be changed back. The FMVExtension "sve2-aes" depends on the ExtensionWithMArch "sve2-aes". Patches like #113281 and #87939 rely on it.

labrinea · 2024-11-08T19:35:39Z

llvm/lib/Target/AArch64/AArch64Features.td

-  "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
+  "Enable SVE AES and quadword SVE polynomial multiply instructions", [FeatureAES]>;
+
+def AliasSVE2AES : ExtensionWithMArch<"sve2-aes", "ALIAS_SVE2AES", "",


If you read at the definition of ExtensionWithMArch the second argument is used to generate the AEK_ field. See inside ./include/llvm/TargetParser/AArch64TargetParserDef.inc in the build directory. We now have this entry:
{"sve2-aes", {}, AArch64::AEK_ALIAS_SVE2AES, "", "An alias of +sve2+sve-aes", "+sve2-aes", "-sve2-aes"},
I think the ALIAS subexpression has no place in AEK names.

labrinea · 2024-11-08T19:38:51Z

llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s

-.arch_extension sve2-aes
-.arch_extension nosve2-aes
+.arch_extension sve-aes
+.arch_extension nosve-aes


Here you are replacing the old test instead of adding a new one. Now the (no)sve2-aes directives are not tested anywhere. Similarly in other files.

That's because all sve2-aes does is enable sve2 and sve-aes (which these instructions are guarded by). The following sequence:

.arch_extension sve2-aes .arch_extension nosve2-aes

Would still allow the use of aesd, because disabling a specific feature does not disable it's dependencies. You raise a good point with this comment, we may need to reconsider if this is the intended behavior.

In either case, I should not have removed the positive tests for sve2-aes so I'll fix that.

all sve2-aes does is enable sve2 and sve-aes

Correct.

disabling a specific feature does not disable it's dependencies

Also correct

To preserve the old semantics of nosve2-aes we need to change the asm parser as follows:
{"sve2-aes", {AArch64::FeatureSVE2, AArch64::FeatureSVEAES}}

I see, thanks.

You may find in useful to look at https://github.com/llvm/llvm-project/pull/110816/files. In order to make nosve2-aes backwards compatible on the command line you need to adjust AArch64::ExtensionSet::disable in TargetParser. Then you can add tests in clang/test/Driver/ for it.

)" This reverts commit da9499e.

labrinea · 2024-11-08T20:08:03Z

clang/lib/Basic/Targets/AArch64.cpp

@@ -769,7 +769,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
      .Case("f32mm", FPU & SveMode && HasMatmulFP32)
      .Case("f64mm", FPU & SveMode && HasMatmulFP64)
      .Case("sve2", FPU & SveMode && HasSVE2)
-      .Case("sve2-pmull128", FPU & SveMode && HasSVE2AES)
+      .Case("sve2-pmull128", FPU & SveMode && HasSVEAES && HasSVE2)


sve2-pmull128 does not exist, this function and the one below need cleanup

This patch essentially re-lands #114293 with the following fixups - `nosve2-aes` should disable the backend feature `FeatureSVEAES` such that the set of existing instructions that this removes is unchanged. - FMV dependencies now use the autogenerated `ExtensionDepencies` structure (since #113281) so we do not require the change to `AArch64FMV.td`.

This patch introduces the amended feature flag for [FEAT_SVE_AES](https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-0-architecture-extension?lang=en#md457-the-armv90-architecture-extension__feat_FEAT_SVE_AES), '**sve-aes**'. The existing flag associated with this feature, 'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for backwards compatibility. The [ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md#aes-extension) documents `__ARM_FEATURE_SVE2_AES`, which was previously defined to 1 when > there is hardware support for the SVE2 AES (FEAT_SVE_AES) instructions and if the associated ACLE intrinsics are available. The front-end has been amended such that it is compatible with +sve2-aes and +sve2+sve-aes.

SpencerAbson requested review from momchil-velikov, Lukacma and CarolineConcatto October 30, 2024 18:43

llvmbot added clang Clang issues not falling into any other category backend:AArch64 clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" labels Oct 30, 2024

[NFC] fix test format

0fc4ce1

SpencerAbson commented Oct 30, 2024

View reviewed changes

llvm/lib/Target/AArch64/AArch64Features.td Outdated Show resolved Hide resolved

llvm/lib/Target/AArch64/AArch64Features.td Show resolved Hide resolved

Update existing intrinsics and AArch64.cpp

f269958

Lukacma reviewed Oct 31, 2024

View reviewed changes

llvm/lib/Target/AArch64/AArch64Features.td Outdated Show resolved Hide resolved

clang/test/Driver/aarch64-implied-sve-features.c Outdated Show resolved Hide resolved

Update predication of effected instructions

aa9e586

llvmbot added the mc Machine (object) code label Oct 31, 2024

SpencerAbson added 2 commits November 1, 2024 09:47

Add RUN line to test lowering from IR

fa51558

Remove change to clang driver test

4520ec4

CarolineConcatto reviewed Nov 1, 2024

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llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td Show resolved Hide resolved

jthackray self-requested a review November 5, 2024 14:12

mgabka reviewed Nov 5, 2024

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llvm/lib/Target/AArch64/AArch64Features.td Outdated Show resolved Hide resolved

Fix FMV dependencies and respond to review comments

ec6f646

SpencerAbson requested a review from JDevlieghere as a code owner November 6, 2024 11:31

llvmbot added the lldb label Nov 6, 2024

Clarify feature descriptions

8562649

CarolineConcatto approved these changes Nov 8, 2024

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Merge branch 'main' into add-sve2-aes-alias

ef249d8

SpencerAbson merged commit da9499e into llvm:main Nov 8, 2024
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labrinea reviewed Nov 8, 2024

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SpencerAbson added a commit that referenced this pull request Nov 8, 2024

Revert "[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114293

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)" This reverts commit da9499e.

labrinea reviewed Nov 8, 2024

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SpencerAbson mentioned this pull request Nov 13, 2024

[AArch64] Make +sve2-aes an alias of +sve2+sve-aes #116026

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[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 #114293

[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 #114293

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[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 #114293

[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 #114293

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