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[AArch64] Guard against getRegisterBitWidth returning zero in vector instr cost. #117749

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merged 1 commit into from
Nov 29, 2024
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[AArch64] Guard against getRegisterBitWidth returning zero in vector instr cost. #117749

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3259,7 +3259,7 @@ InstructionCost AArch64TTIImpl::getVectorInstrCostHelper(
auto RegWidth =
getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
.getFixedValue();
return (Idx == 0 || (Idx * EltSz) % RegWidth == 0);
return Idx == 0 || (RegWidth != 0 && (Idx * EltSz) % RegWidth == 0);
};

// Check if the type constraints on input vector type and result scalar type
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18 changes: 18 additions & 0 deletions llvm/test/Analysis/CostModel/AArch64/extract_float_streaming.ll
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@@ -0,0 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=aarch64-unknown-linux -mattr=+sme | FileCheck %s

define double @extract_case7(<4 x double> %a) "aarch64_pstate_sm_enabled" {
; CHECK-LABEL: 'extract_case7'
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %0 = extractelement <4 x double> %a, i32 1
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %1 = extractelement <4 x double> %a, i32 2
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res = fmul double %0, %1
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret double %res
;
entry:
%1 = extractelement <4 x double> %a, i32 1
%2 = extractelement <4 x double> %a, i32 2
%res = fmul double %1, %2
ret double %res
}

declare void @foo(double)