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[HEXAGON] Add support to lower "FREEZE a half(f16)" instruction on Hexagon and fix the isel-buildvector-v2f16.ll assertion #130977

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Merged
merged 1 commit into from
Mar 12, 2025
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[HEXAGON] Add support to lower "FREEZE a half(f16)" instruction on Hexagon and fix the isel-buildvector-v2f16.ll assertion #130977

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1 change: 1 addition & 0 deletions llvm/lib/Target/Hexagon/HexagonISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -362,6 +362,7 @@ class HexagonTargetLowering : public TargetLowering {
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
return AtomicExpansionKind::LLSC;
}
bool softPromoteHalfType() const override { return true; }
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I suppose this is technically an ABI change, thus precluding a backport to 20.1.1, right?

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@tstellar is this kind of change one that prevents backporting? Or requires a 20.2.x?


private:
void initializeHVXLowering();
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22 changes: 11 additions & 11 deletions llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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Expand Up @@ -1618,17 +1618,6 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG)
for (unsigned i = 0; i != Size; ++i)
Ops.push_back(Op.getOperand(i));

// First, split the BUILD_VECTOR for vector pairs. We could generate
// some pairs directly (via splat), but splats should be generated
// by the combiner prior to getting here.
if (VecTy.getSizeInBits() == 16*Subtarget.getVectorLength()) {
ArrayRef<SDValue> A(Ops);
MVT SingleTy = typeSplit(VecTy).first;
SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG);
SDValue V1 = buildHvxVectorReg(A.drop_front(Size/2), dl, SingleTy, DAG);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
}

if (VecTy.getVectorElementType() == MVT::i1)
return buildHvxVectorPred(Ops, dl, VecTy, DAG);

Expand All @@ -1645,6 +1634,17 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG)
return DAG.getBitcast(tyVector(VecTy, MVT::f16), T0);
}

// First, split the BUILD_VECTOR for vector pairs. We could generate
// some pairs directly (via splat), but splats should be generated
// by the combiner prior to getting here.
if (VecTy.getSizeInBits() == 16 * Subtarget.getVectorLength()) {
ArrayRef<SDValue> A(Ops);
MVT SingleTy = typeSplit(VecTy).first;
SDValue V0 = buildHvxVectorReg(A.take_front(Size / 2), dl, SingleTy, DAG);
SDValue V1 = buildHvxVectorReg(A.drop_front(Size / 2), dl, SingleTy, DAG);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
}

return buildHvxVectorReg(Ops, dl, VecTy, DAG);
}

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44 changes: 44 additions & 0 deletions llvm/test/CodeGen/Hexagon/fp16-promote.ll
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@@ -0,0 +1,44 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon < %s | FileCheck %s

define half @freeze_half_undef() nounwind {
; CHECK-LABEL: freeze_half_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: call __truncsfhf2
; CHECK-NEXT: r0 = #0
; CHECK-NEXT: allocframe(#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: call __extendhfsf2
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: call __truncsfhf2
; CHECK-NEXT: r0 = sfadd(r0,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
; CHECK-NEXT: }
%y1 = freeze half undef
%t1 = fadd half %y1, %y1
ret half %t1
}

define half @freeze_half_poison(half %maybe.poison) {
; CHECK-LABEL: freeze_half_poison:
; CHECK: // %bb.0:
; CHECK: {
; CHECK-NEXT: call __extendhfsf2
; CHECK-NEXT: allocframe(r29,#0):raw
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: call __truncsfhf2
; CHECK-NEXT: r0 = sfadd(r0,r0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
; CHECK-NEXT: }
%y1 = freeze half %maybe.poison
%t1 = fadd half %y1, %y1
ret half %t1
}