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[AMDGPU] Fix SIFoldOperandsImpl::tryFoldZeroHighBits when met non-reg src1 operand. #133761

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merged 3 commits into from
Apr 1, 2025
Merged

[AMDGPU] Fix SIFoldOperandsImpl::tryFoldZeroHighBits when met non-reg src1 operand. #133761

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885dcd8
[AMDGPU] Fix SIFoldOperandsImpl::tryFoldZeroHighBits when met non-reg…
vpykhtin Mar 31, 2025
40838d8
per review fixes.
vpykhtin Apr 1, 2025
9b01a20
removed extra lines
vpykhtin Apr 1, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1453,7 +1453,7 @@ bool SIFoldOperandsImpl::tryFoldZeroHighBits(MachineInstr &MI) const {
return false;

std::optional<int64_t> Src0Imm = getImmOrMaterializedImm(MI.getOperand(1));
if (!Src0Imm || *Src0Imm != 0xffff)
if (!Src0Imm || *Src0Imm != 0xffff || !MI.getOperand(2).isReg())
return false;

Register Src1 = MI.getOperand(2).getReg();
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17 changes: 17 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1101 -run-pass si-fold-operands %s -o - | FileCheck %s
---
name: test_tryFoldZeroHighBits_skips_nonreg
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_tryFoldZeroHighBits_skips_nonreg
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 65535, 0, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%1:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
%2:vgpr_32 = V_AND_B32_e64 65535, %1.sub0, implicit $exec
S_NOP 0, implicit %2
...
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