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svs-quic merged 4 commits into from
May 10, 2025
Merged

[RISCV] Add some compress patterns for Xqci instructions #139273

svs-quic merged 4 commits into from
May 10, 2025

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@svs-quic svs-quic commented May 9, 2025

There are some patterns that have not been added that will need changes to the CompressInstEmitter. Those will be handled in later patches.

@svs-quic
[RISCV] Add some compress patterns for Xqci instructions
5a14fe8 
There are some patterns that have not been added that will need changes
to the CompressInstEmitter. Those will be handled in later patches.
@llvmbot llvmbot added backend:RISC-V llvm:mc Machine (object) code labels May 9, 2025
@svs-quic svs-quic requested review from hchandel, lenary, pgodeq and topperc May 9, 2025 14:36
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llvmbot commented May 9, 2025 •
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@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

Changes

There are some patterns that have not been added that will need changes to the CompressInstEmitter. Those will be handled in later patches.

Full diff: https://github.com/llvm/llvm-project/pull/139273.diff

7 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+32)
  • (modified) llvm/test/MC/RISCV/xqcibm-valid.s (+23-10)
  • (modified) llvm/test/MC/RISCV/xqcilb-relocations.s (+4)
  • (modified) llvm/test/MC/RISCV/xqcilb-valid.s (+18-7)
  • (modified) llvm/test/MC/RISCV/xqcili-relocations.s (+4)
  • (modified) llvm/test/MC/RISCV/xqcili-valid.s (+14-5)
  • (modified) llvm/test/MC/RISCV/xqcilia-valid.s (+14-2)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 5ff140ce2e4b4..a8ebbd9090cfb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1407,3 +1407,35 @@ let Predicates = [HasVendorXqcibm, IsRV32] in {
 def : CompressPat<(QC_EXTU GPRNoX0:$rd, GPRNoX0:$rd, uimm5ge6_plus1:$width, 0),
                   (QC_C_EXTU GPRNoX0:$rd, uimm5ge6_plus1:$width)>;
 }
+
+let Predicates = [HasVendorXqcibm, HasStdExtZbs, IsRV32] in {
+def : CompressPat<(BSETI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$shamt),
+                  (QC_C_BSETI GPRC:$rs1, uimmlog2xlennonzero:$shamt)>;
+def : CompressPat<(BEXTI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$shamt),
+                  (QC_C_BEXTI GPRC:$rs1, uimmlog2xlennonzero:$shamt)>;
+} // Predicates = [HasVendorXqcibm, HasStdExtZbs, IsRV32]
+
+let Predicates = [HasVendorXqcilb, IsRV32] in {
+def : CompressPat<(QC_E_J bare_simm12_lsb0:$offset),
+                  (C_J bare_simm12_lsb0:$offset)>;
+
+let isCompressOnly = true in
+def : CompressPat<(QC_E_JAL bare_simm12_lsb0:$offset),
+                  (C_JAL bare_simm12_lsb0:$offset)>;
+} // Predicates = [HasVendorXqcilb, IsRV32]
+
+let Predicates = [HasVendorXqcili, IsRV32] in {
+def : CompressPat<(QC_LI GPRNoX0:$rd, simm6:$imm),
+                  (C_LI GPRNoX0:$rd, simm6:$imm)>;
+
+let isCompressOnly = true in
+def : CompressPat<(QC_E_LI GPRNoX0:$rd, simm6:$imm),
+                  (C_LI GPRNoX0:$rd, simm6:$imm)>;
+} // Predicates = [HasVendorXqcili, IsRV32]
+
+let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32] in {
+def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
+                  (C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>;
+def : CompressPat<(QC_E_ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
+                  (C_ANDI GPRC:$rs1, simm6:$imm)>;
+} // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]
diff --git a/llvm/test/MC/RISCV/xqcibm-valid.s b/llvm/test/MC/RISCV/xqcibm-valid.s
index e549d5fdfd7d2..4bbf2bc2b01d0 100644
--- a/llvm/test/MC/RISCV/xqcibm-valid.s
+++ b/llvm/test/MC/RISCV/xqcibm-valid.s
@@ -1,13 +1,14 @@
 # Xqcibm - Qualcomm uC Bit Manipulation Extension
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm -M no-aliases -show-encoding \
+# Zbs is needed for checking compress instructions patterns for bexti/bseti
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm,+zbs -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-xqcibm -M no-aliases --no-print-imm-hex -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm,+zbs  < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqcibm,+zbs -M no-aliases --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm,+zbs  -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-xqcibm --no-print-imm-hex -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm,+zbs < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqcibm,+zbs --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-INST: qc.compress2   t2, t0
@@ -110,11 +111,13 @@ qc.extdpr x1, x4, x15
 # CHECK-ENC: encoding: [0x0b,0x33,0x9c,0x13]
 qc.extdprh x6, x24, x25
 
-# CHECK-INST: qc.c.bexti  s1, 8
+# CHECK-NOALIAS: qc.c.bexti  s1, 8
+# CHECK-ALIAS: bexti s1, s1, 8
 # CHECK-ENC: encoding: [0xa1,0x90]
 qc.c.bexti x9, 8
 
-# CHECK-INST: qc.c.bseti a2, 16
+# CHECK-NOALIAS: qc.c.bseti a2, 16
+# CHECK-ALIAS: bseti a2, a2, 16
 # CHECK-ENC: encoding: [0x41,0x96]
 qc.c.bseti x12, 16
 
@@ -123,9 +126,19 @@ qc.c.bseti x12, 16
 # CHECK-ENC: encoding: [0xfe,0x17]
 qc.c.extu x15, 32
 
-# Check that compress pattern for qc.extu works
+# Check that compress patterns work as expected
 
 # CHECK-NOALIAS: qc.c.extu  a1, 11
 # CHECK-ALIAS: qc.extu a1, a1, 11, 0
 # CHECK-ENC: encoding: [0xaa,0x15]
-qc.extu x11, x11, 11, 0	
+qc.extu x11, x11, 11, 0
+
+# CHECK-NOALIAS: qc.c.bexti  s1, 8
+# CHECK-ALIAS: bexti s1, s1, 8
+# CHECK-ENC-ZBS: encoding: [0xa1,0x90]
+bexti x9, x9, 8
+
+# CHECK-NOALIAS: qc.c.bseti a2, 16
+# CHECK-ALIAS: bseti a2, a2, 16
+# CHECK-ENC: encoding: [0x41,0x96]
+bseti x12, x12, 16
diff --git a/llvm/test/MC/RISCV/xqcilb-relocations.s b/llvm/test/MC/RISCV/xqcilb-relocations.s
index 66f052283812e..0a5b788a110da 100644
--- a/llvm/test/MC/RISCV/xqcilb-relocations.s
+++ b/llvm/test/MC/RISCV/xqcilb-relocations.s
@@ -9,6 +9,8 @@
 
 .text
 
+.option exact
+
 qc.e.j foo
 # RELOC: R_RISCV_CUSTOM195 foo 0x0
 # INSTR: qc.e.j foo
@@ -33,6 +35,8 @@ qc.e.j .L1
 qc.e.jal .L1
 # INSTR:qc.e.jal .L1
 
+.option noexact
+
 .L1:
   ret
 
diff --git a/llvm/test/MC/RISCV/xqcilb-valid.s b/llvm/test/MC/RISCV/xqcilb-valid.s
index 2b871f085438f..4653bfe958772 100644
--- a/llvm/test/MC/RISCV/xqcilb-valid.s
+++ b/llvm/test/MC/RISCV/xqcilb-valid.s
@@ -1,14 +1,14 @@
 # Xqcilb - Qualcomm uC Long Branch Extension
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcilb -M no-aliases --no-print-imm-hex -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-NOALIAS %s
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcilb --no-print-imm-hex -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-ALIAS %s
 
 # CHECK-INST: qc.e.j  -2147483648
 # CHECK-OBJ: qc.e.j  0x80000000
@@ -20,7 +20,18 @@ qc.e.j  -2147483648
 # CHECK-ENC: encoding: [0x9f,0xcc,0x0e,0xfe,0xff,0x7f]
 qc.e.jal 2147483640
 
-# CHECK-INST: qc.e.jal -116
-# CHECK-OBJ: qc.e.jal 0xffffff98
-# CHECK-ENC: encoding: [0x9f,0xc6,0x0e,0xf8,0xff,0xff]
+# Check that compress patterns work as expected
+
+# CHECK-NOALIAS: c.jal -116
+# CHECK-ALIAS: jal -116
+# CHECK-OBJ-NOALIAS: c.jal 0xffffff98
+# CHECK-OBJ-ALIAS: jal 0xffffff98
+# CHECK-ENC: encoding: [0x71,0x37]
 qc.e.jal 0xffffff8c
+
+# CHECK-NOALIAS: c.j 1024
+# CHECK-ALIAS: j 1024
+# CHECK-OBJ-NOALIAS: c.j 0x40e
+# CHECK-OBJ-ALIAS: j 0x40e
+# CHECK-ENC: encoding: [0x01,0xa1]
+qc.e.j 1024
diff --git a/llvm/test/MC/RISCV/xqcili-relocations.s b/llvm/test/MC/RISCV/xqcili-relocations.s
index b7fcb405d27bb..9c709e68334cd 100644
--- a/llvm/test/MC/RISCV/xqcili-relocations.s
+++ b/llvm/test/MC/RISCV/xqcili-relocations.s
@@ -9,6 +9,8 @@
 
 .text
 
+.option exact
+
 qc.li x4, %qc.abs20(foo)
 # RELOC: R_RISCV_CUSTOM192 foo 0x0
 # INSTR: qc.li tp, %qc.abs20(foo)
@@ -33,6 +35,8 @@ qc.li x7, %qc.abs20(.L1)
 qc.e.li x6, .L1
 # INSTR: qc.e.li t1, .L1
 
+.option noexact
+
 .L1:
   ret
 
diff --git a/llvm/test/MC/RISCV/xqcili-valid.s b/llvm/test/MC/RISCV/xqcili-valid.s
index c2f1bc2bd0c35..aa2898da3173a 100644
--- a/llvm/test/MC/RISCV/xqcili-valid.s
+++ b/llvm/test/MC/RISCV/xqcili-valid.s
@@ -1,21 +1,18 @@
 # Xqcili - Qualcomm uC Load Large Immediate Extension
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
 
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcili < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcili -M no-aliases --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
 
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcili < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcili --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: qc.e.li a0, -1
-# CHECK-ENC: encoding: [0x1f,0x05,0xff,0xff,0xff,0xff]
-qc.e.li x10, 4294967295
 
 # CHECK-INST: qc.e.li a0, -2147483648
 # CHECK-ENC: encoding: [0x1f,0x05,0x00,0x00,0x00,0x80]
@@ -44,3 +41,15 @@ qc.li x10, 12345
 # CHECK-INST: qc.li   a0, -12346
 # CHECK-ENC: encoding: [0x1b,0xf5,0xc6,0xcf]
 qc.li x10, -12346
+
+# Check that compress patterns work as expected
+
+# CHECK-ALIAS: li a0, -1
+# CHECK-NOALIAS: c.li a0, -1
+# CHECK-ENC: encoding: [0x7d,0x55]
+qc.e.li x10, 4294967295
+
+# CHECK-ALIAS: li a0, 31
+# CHECK-NOALIAS: c.li a0, 31
+# CHECK-ENC: encoding: [0x7d,0x45]
+qc.li x10, 31
diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s
index 03b20b04e3032..1e4f855cb2b47 100644
--- a/llvm/test/MC/RISCV/xqcilia-valid.s
+++ b/llvm/test/MC/RISCV/xqcilia-valid.s
@@ -1,11 +1,11 @@
 # Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcilia -M no-aliases --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
@@ -80,3 +80,15 @@ qc.e.xori x10, x9, -33554432
 # CHECK-INST: qc.e.xori       a0, s1, 33554431
 # CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x3f,0xff,0x7f]
 qc.e.xori x10, x9, 33554431
+
+# Check that compress patterns work as expected
+
+# CHECK-ALIAS: addi t0, t0, 20
+# CHECK-NOALIAS: c.addi t0, 20
+# CHECK-ENC: encoding: [0xd1,0x02]
+qc.e.addi x5, x5, 20
+
+# CHECK-ALIAS: andi s1, s1, -10
+# CHECK-NOALIAS: c.andi s1, -10
+# CHECK-ENC: encoding: [0xd9,0x98]
+qc.e.andi x9, x9, -10

lenary
lenary reviewed May 9, 2025
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lenary
lenary reviewed May 10, 2025
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svs-quic commented May 10, 2025

Build failure unrelated.

lenary
lenary approved these changes May 10, 2025
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LGTM

@svs-quic svs-quic merged commit 04cb2b3 into llvm:main May 10, 2025
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@svs-quic svs-quic deleted the xqcicomp branch May 12, 2025 05:22
@MaskRay MaskRay mentioned this pull request Jul 10, 2025
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@lenary lenary lenary approved these changes

@topperc topperc Awaiting requested review from topperc

@pgodeq pgodeq Awaiting requested review from pgodeq

@hchandel hchandel Awaiting requested review from hchandel

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