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[CIR][NFC] Use getType() instead of more verbose getResult().getType() #143024

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Merged
merged 1 commit into from
Jun 6, 2025
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[CIR][NFC] Use getType() instead of more verbose getResult().getType() #143024

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5 changes: 0 additions & 5 deletions clang/include/clang/CIR/Dialect/IR/CIROps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1778,11 +1778,6 @@ def GetMemberOp : CIR_Op<"get_member"> {

/// Return the record type pointed by the base pointer.
cir::PointerType getAddrTy() { return getAddr().getType(); }

/// Return the result type.
cir::PointerType getResultTy() {
return getResult().getType();
}
}];

let hasVerifier = 1;
Expand Down
10 changes: 5 additions & 5 deletions clang/lib/CIR/Dialect/IR/CIRDialect.cpp
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Expand Up @@ -287,7 +287,7 @@ LogicalResult cir::ContinueOp::verify() {
//===----------------------------------------------------------------------===//

LogicalResult cir::CastOp::verify() {
mlir::Type resType = getResult().getType();
mlir::Type resType = getType();
mlir::Type srcType = getSrc().getType();

if (mlir::isa<cir::VectorType>(srcType) &&
Expand Down Expand Up @@ -445,7 +445,7 @@ static Value tryFoldCastChain(cir::CastOp op) {
}

OpFoldResult cir::CastOp::fold(FoldAdaptor adaptor) {
if (getSrc().getType() == getResult().getType()) {
if (getSrc().getType() == getType()) {
switch (getKind()) {
case cir::CastKind::integral: {
// TODO: for sign differences, it's possible in certain conditions to
Expand Down Expand Up @@ -1447,7 +1447,7 @@ LogicalResult cir::ShiftOp::verify() {
if (op0VecTy.getSize() != op1VecTy.getSize())
return emitOpError() << "input vector types must have the same size";

auto opResultTy = mlir::dyn_cast<cir::VectorType>(getResult().getType());
auto opResultTy = mlir::dyn_cast<cir::VectorType>(getType());
if (!opResultTy)
return emitOpError() << "the type of the result must be a vector "
<< "if it is vector shift";
Expand Down Expand Up @@ -1520,7 +1520,7 @@ LogicalResult cir::GetMemberOp::verify() {
if (recordTy.getMembers().size() <= getIndex())
return emitError() << "member index out of bounds";

if (recordTy.getMembers()[getIndex()] != getResultTy().getPointee())
if (recordTy.getMembers()[getIndex()] != getType().getPointee())
return emitError() << "member type mismatch";

return mlir::success();
Expand All @@ -1534,7 +1534,7 @@ LogicalResult cir::VecCreateOp::verify() {
// Verify that the number of arguments matches the number of elements in the
// vector, and that the type of all the arguments matches the type of the
// elements in the vector.
const VectorType vecTy = getResult().getType();
const cir::VectorType vecTy = getType();
if (getElements().size() != vecTy.getSize()) {
return emitOpError() << "operand count of " << getElements().size()
<< " doesn't match vector type " << vecTy
Expand Down
2 changes: 1 addition & 1 deletion clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
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Expand Up @@ -74,7 +74,7 @@ bool cir::LoadOp::canUsesBeRemoved(
return false;
Value blockingUse = (*blockingUses.begin())->get();
return blockingUse == slot.ptr && getAddr() == slot.ptr &&
getResult().getType() == slot.elemType;
getType() == slot.elemType;
}

DeletionKind cir::LoadOp::removeBlockingUses(
Expand Down
20 changes: 9 additions & 11 deletions clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
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Expand Up @@ -105,7 +105,7 @@ static mlir::Value emitFromMemory(mlir::ConversionPatternRewriter &rewriter,
cir::LoadOp op, mlir::Value value) {

// TODO(cir): Handle other types similarly to clang's codegen EmitFromMemory
if (auto boolTy = mlir::dyn_cast<cir::BoolType>(op.getResult().getType())) {
if (auto boolTy = mlir::dyn_cast<cir::BoolType>(op.getType())) {
// Create a cast value from specified size in datalayout to i1
assert(value.getType().isInteger(dataLayout.getTypeSizeInBits(boolTy)));
return createIntCast(rewriter, value, rewriter.getI1Type());
Expand Down Expand Up @@ -424,7 +424,7 @@ mlir::LogicalResult CIRToLLVMCastOpLowering::matchAndRewrite(
}
case cir::CastKind::integral: {
mlir::Type srcType = castOp.getSrc().getType();
mlir::Type dstType = castOp.getResult().getType();
mlir::Type dstType = castOp.getType();
mlir::Value llvmSrcVal = adaptor.getOperands().front();
mlir::Type llvmDstType = getTypeConverter()->convertType(dstType);
cir::IntType srcIntType =
Expand All @@ -439,11 +439,10 @@ mlir::LogicalResult CIRToLLVMCastOpLowering::matchAndRewrite(
}
case cir::CastKind::floating: {
mlir::Value llvmSrcVal = adaptor.getOperands().front();
mlir::Type llvmDstTy =
getTypeConverter()->convertType(castOp.getResult().getType());
mlir::Type llvmDstTy = getTypeConverter()->convertType(castOp.getType());

mlir::Type srcTy = elementTypeIfVector(castOp.getSrc().getType());
mlir::Type dstTy = elementTypeIfVector(castOp.getResult().getType());
mlir::Type dstTy = elementTypeIfVector(castOp.getType());

if (!mlir::isa<cir::CIRFPTypeInterface>(dstTy) ||
!mlir::isa<cir::CIRFPTypeInterface>(srcTy))
Expand Down Expand Up @@ -531,8 +530,7 @@ mlir::LogicalResult CIRToLLVMCastOpLowering::matchAndRewrite(
mlir::Type dstTy = castOp.getType();
mlir::Value llvmSrcVal = adaptor.getOperands().front();
mlir::Type llvmDstTy = getTypeConverter()->convertType(dstTy);
if (mlir::cast<cir::IntType>(
elementTypeIfVector(castOp.getResult().getType()))
if (mlir::cast<cir::IntType>(elementTypeIfVector(castOp.getType()))
.isSigned())
rewriter.replaceOpWithNewOp<mlir::LLVM::FPToSIOp>(castOp, llvmDstTy,
llvmSrcVal);
Expand Down Expand Up @@ -649,8 +647,8 @@ mlir::LogicalResult CIRToLLVMAllocaOpLowering::matchAndRewrite(
op.getLoc(), typeConverter->convertType(rewriter.getIndexType()), 1);
mlir::Type elementTy =
convertTypeForMemory(*getTypeConverter(), dataLayout, op.getAllocaType());
mlir::Type resultTy = convertTypeForMemory(*getTypeConverter(), dataLayout,
op.getResult().getType());
mlir::Type resultTy =
convertTypeForMemory(*getTypeConverter(), dataLayout, op.getType());

assert(!cir::MissingFeatures::addressSpace());
assert(!cir::MissingFeatures::opAllocaAnnotations());
Expand Down Expand Up @@ -722,8 +720,8 @@ mlir::LogicalResult CIRToLLVMCallOpLowering::matchAndRewrite(
mlir::LogicalResult CIRToLLVMLoadOpLowering::matchAndRewrite(
cir::LoadOp op, OpAdaptor adaptor,
mlir::ConversionPatternRewriter &rewriter) const {
const mlir::Type llvmTy = convertTypeForMemory(
*getTypeConverter(), dataLayout, op.getResult().getType());
const mlir::Type llvmTy =
convertTypeForMemory(*getTypeConverter(), dataLayout, op.getType());
assert(!cir::MissingFeatures::opLoadStoreMemOrder());
std::optional<size_t> opAlign = op.getAlignment();
unsigned alignment =
Expand Down
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