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[X86][GlobalIsel] G_BITCAST support #144473

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[X86][GlobalIsel] G_BITCAST support #144473

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7e9a3d8
add bitcast
Jun 17, 2025
7c9a415
fix test
Jun 19, 2025
04abe43
fix review comment
Jun 19, 2025
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18 changes: 18 additions & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -669,6 +669,8 @@ bool X86LegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
return legalizeSITOFP(MI, MRI, Helper);
case TargetOpcode::G_FPTOSI:
return legalizeFPTOSI(MI, MRI, Helper);
case TargetOpcode::G_BITCAST:
return legalizeBitcast(MI, MRI, Helper);
}
llvm_unreachable("expected switch to return");
}
Expand Down Expand Up @@ -835,6 +837,22 @@ bool X86LegalizerInfo::legalizeNarrowingStore(MachineInstr &MI,
return true;
}

bool X86LegalizerInfo::legalizeBitcast(MachineInstr &MI,
MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
bool isCopy =
(SrcTy == DstTy) || (SrcTy.getSizeInBits() == DstTy.getSizeInBits());
if (isCopy) {
MIRBuilder.buildCopy(DstReg, SrcReg);
MI.eraseFromParent();
return true;
}
// For Vectors specific bitcasts
return Helper.lowerBitcast(MI) == LegalizerHelper::LegalizeResult::Legalized;
}

bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
return true;
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
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Expand Up @@ -54,6 +54,8 @@ class X86LegalizerInfo : public LegalizerInfo {

bool legalizeFPTOSI(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
bool legalizeBitcast(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
};
} // namespace llvm
#endif
39 changes: 36 additions & 3 deletions llvm/test/CodeGen/X86/bitcast.ll
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@@ -1,24 +1,57 @@
; RUN: llc < %s -mtriple=i686--
; RUN: llc < %s -mtriple=x86_64--
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64--| FileCheck %s -check-prefixes=X64
; RUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=0 | FileCheck %s -check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=X64
; PR1033
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better to create a new isel-bitcast.ll test file instead with full dag/fastisel/gisel coverage (see other isel-* files for examples)

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@mahesh-attarde mahesh-attarde Jun 19, 2025 •
edited
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#144928 Added Test


define i64 @test1(double %t) {
; X64-LABEL: test1:
; X64: # %bb.0:
; X64-NEXT: movq %xmm0, %rax
; X64-NEXT: retq
%u = bitcast double %t to i64 ; <i64> [#uses=1]
ret i64 %u
}

define double @test2(i64 %t) {
; X86-LABEL: test2:
; X86: # %bb.0:
; X86-NEXT: fldl {{[0-9]+}}(%esp)
; X86-NEXT: retl
;
; X64-LABEL: test2:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %xmm0
; X64-NEXT: retq
%u = bitcast i64 %t to double ; <double> [#uses=1]
ret double %u
}

define i32 @test3(float %t) {
; X86-LABEL: test3:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: test3:
; X64: # %bb.0:
; X64-NEXT: movd %xmm0, %eax
; X64-NEXT: retq
%u = bitcast float %t to i32 ; <i32> [#uses=1]
ret i32 %u
}

define float @test4(i32 %t) {
; X86-LABEL: test4:
; X86: # %bb.0:
; X86-NEXT: flds {{[0-9]+}}(%esp)
; X86-NEXT: retl
;
; X64-LABEL: test4:
; X64: # %bb.0:
; X64-NEXT: movd %edi, %xmm0
; X64-NEXT: retq
%u = bitcast i32 %t to float ; <float> [#uses=1]
ret float %u
}

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