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[X86] combineStore - remove rangedata when converting 64-bit copies to f64 load/store #147904

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Merged
merged 1 commit into from
Jul 10, 2025
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[X86] combineStore - remove rangedata when converting 64-bit copies to f64 load/store #147904

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4 changes: 4 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -53574,6 +53574,10 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,

SDLoc LdDL(Ld);
SDLoc StDL(N);

// Remove any range metadata as we're converting to f64 load/store.
Ld->getMemOperand()->clearRanges();

// Lower to a single movq load/store pair.
SDValue NewLd = DAG.getLoad(MVT::f64, LdDL, Ld->getChain(),
Ld->getBasePtr(), Ld->getMemOperand());
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19 changes: 19 additions & 0 deletions llvm/test/CodeGen/X86/pr147781.ll
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@@ -0,0 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-pc-windows-gnu -verify-machineinstrs | FileCheck %s

; Ensure i64 !range data is stripped when converting to f64 load/store.
define void @test(ptr %p, ptr %p2) #0 {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, (%eax)
; CHECK-NEXT: retl
%val = load i64, ptr %p, align 8, !range !0
store i64 %val, ptr %p2, align 8
ret void
}

attributes #0 = { "target-cpu"="pentium4" }
!0 = !{i64 1, i64 0}
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