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33 changes: 33 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -22328,6 +22328,37 @@ static SDValue performExtBinopLoadFold(SDNode *N, SelectionDAG &DAG) {
return DAG.getNode(N->getOpcode(), DL, VT, Ext0, NShift);
}

// Attempt to combine the following patterns:
// SUB x, (CSET LO, (CMP a, b)) -> SBC x, 0, (CMP a, b)
// SUB (SUB x, y), (CSET LO, (CMP a, b)) -> SBC x, y, (CMP a, b)
// The CSET may be preceded by a ZEXT.
static SDValue performSubWithBorrowCombine(SDNode *N, SelectionDAG &DAG) {
if (N->getOpcode() != ISD::SUB)
return SDValue();

EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
return SDValue();

SDValue N1 = N->getOperand(1);
if (N1.getOpcode() == ISD::ZERO_EXTEND && N1.hasOneUse())
N1 = N1.getOperand(0);
if (!N1.hasOneUse() || getCSETCondCode(N1) != AArch64CC::LO)
return SDValue();

SDValue Flags = N1.getOperand(3);
if (Flags.getOpcode() != AArch64ISD::SUBS)
return SDValue();

SDLoc DL(N);
SDValue N0 = N->getOperand(0);
if (N0->getOpcode() == ISD::SUB)
return DAG.getNode(AArch64ISD::SBC, DL, VT, N0.getOperand(0),
N0.getOperand(1), Flags);
return DAG.getNode(AArch64ISD::SBC, DL, VT, N0, DAG.getConstant(0, DL, VT),
Flags);
}

static SDValue performAddSubCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
// Try to change sum of two reductions.
Expand All @@ -22349,6 +22380,8 @@ static SDValue performAddSubCombine(SDNode *N,
return Val;
if (SDValue Val = performAddSubIntoVectorOp(N, DCI.DAG))
return Val;
if (SDValue Val = performSubWithBorrowCombine(N, DCI.DAG))
return Val;

if (SDValue Val = performExtBinopLoadFold(N, DCI.DAG))
return Val;
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