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[AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short #167798

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mssefat merged 1 commit into from
Dec 12, 2025
Merged

[AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short #167798

mssefat merged 1 commit into from
Dec 12, 2025

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@mssefat mssefat commented Nov 13, 2025 •
edited by arsenm
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This patch adds register bank legalization support for buffer load byte and short operations in the AMDGPU GlobalISel pipeline.

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llvmbot commented Nov 13, 2025 •
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@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Syadus Sefat (mssefat)

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[AMDGPU][GlobalISel] Add register bank legalization for G_AMDGPU_BUFFER_LOAD_USHORT, G_AMDGPU_BUFFER_LOAD_UBYTE, G_AMDGPU_BUFFER_LOAD_SSHORT, G_AMDGPU_BUFFER_LOAD_SBYTE

This patch adds register bank legalization support for buffer load byte and short operations in the AMDGPU GlobalISel pipeline.

Full diff: https://github.com/llvm/llvm-project/pull/167798.diff

6 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+6)
  • (added) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.i8u8i16u16.ll (+194)
  • (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll (+3-3)
  • (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll (+1-1)
  • (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll (+3-3)
  • (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll (+1-1)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 90114e44f1a48..9960a37e63620 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -890,6 +890,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Div(B128, {{VgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}})
       .Uni(B128, {{UniInVgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}});
 
+  addRulesForGOpcs({G_AMDGPU_BUFFER_LOAD_USHORT, G_AMDGPU_BUFFER_LOAD_UBYTE,
+                    G_AMDGPU_BUFFER_LOAD_SSHORT, G_AMDGPU_BUFFER_LOAD_SBYTE},
+                   StandardB)
+      .Div(B32, {{VgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}})
+      .Uni(B32, {{UniInVgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}});
+
   addRulesForGOpcs({G_AMDGPU_BUFFER_STORE})
       .Any({{S32}, {{}, {Vgpr32, SgprV4S32, Vgpr32, Vgpr32, Sgpr32}}});
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.i8u8i16u16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.i8u8i16u16.ll
new file mode 100644
index 0000000000000..036d7cd2e79f5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.i8u8i16u16.ll
@@ -0,0 +1,194 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s
+
+define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    buffer_load_u8 v0, v0, s[0:3], s4 offen
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %zext = zext i8 %val to i32
+  %cast = bitcast i32 %zext to float
+  ret float %cast
+}
+
+define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    buffer_load_i8 v0, v0, s[0:3], s4 offen
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %sext = sext i8 %val to i32
+  %cast = bitcast i32 %sext to float
+  ret float %cast
+}
+
+define amdgpu_ps float @raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    buffer_load_u16 v0, v0, s[0:3], s4 offen
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %zext = zext i16 %val to i32
+  %cast = bitcast i32 %zext to float
+  ret float %cast
+}
+
+define amdgpu_ps float @raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    buffer_load_i16 v0, v0, s[0:3], s4 offen
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %sext = sext i16 %val to i32
+  %cast = bitcast i32 %sext to float
+  ret float %cast
+}
+
+define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset_zext(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset_zext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1
+; GFX12-NEXT:    s_mov_b32 s2, exec_lo
+; GFX12-NEXT:  .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_readfirstlane_b32 s4, v5
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_readfirstlane_b32 s5, v6
+; GFX12-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX12-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX12-NEXT:    s_wait_alu 0xf1ff
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
+; GFX12-NEXT:    v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
+; GFX12-NEXT:    s_and_b32 s1, vcc_lo, s1
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    s_and_saveexec_b32 s1, s1
+; GFX12-NEXT:    buffer_load_u8 v6, v4, s[4:7], s0 offen
+; GFX12-NEXT:    ; implicit-def: $vgpr5
+; GFX12-NEXT:    ; implicit-def: $vgpr4
+; GFX12-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX12-NEXT:    s_xor_b32 exec_lo, exec_lo, s1
+; GFX12-NEXT:    s_cbranch_execnz .LBB4_1
+; GFX12-NEXT:  ; %bb.2:
+; GFX12-NEXT:    s_mov_b32 exec_lo, s2
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_mov_b32_e32 v0, v6
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %zext = zext i8 %val to i32
+  %cast = bitcast i32 %zext to float
+  ret float %cast
+}
+
+define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset_sext(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset_sext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1
+; GFX12-NEXT:    s_mov_b32 s2, exec_lo
+; GFX12-NEXT:  .LBB5_1: ; =>This Inner Loop Header: Depth=1
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_readfirstlane_b32 s4, v5
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_readfirstlane_b32 s5, v6
+; GFX12-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX12-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX12-NEXT:    s_wait_alu 0xf1ff
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
+; GFX12-NEXT:    v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
+; GFX12-NEXT:    s_and_b32 s1, vcc_lo, s1
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    s_and_saveexec_b32 s1, s1
+; GFX12-NEXT:    buffer_load_i8 v6, v4, s[4:7], s0 offen
+; GFX12-NEXT:    ; implicit-def: $vgpr5
+; GFX12-NEXT:    ; implicit-def: $vgpr4
+; GFX12-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX12-NEXT:    s_xor_b32 exec_lo, exec_lo, s1
+; GFX12-NEXT:    s_cbranch_execnz .LBB5_1
+; GFX12-NEXT:  ; %bb.2:
+; GFX12-NEXT:    s_mov_b32 exec_lo, s2
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_mov_b32_e32 v0, v6
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %sext = sext i8 %val to i32
+  %cast = bitcast i32 %sext to float
+  ret float %cast
+}
+
+define amdgpu_ps float @raw_buffer_load_i16__vgpr_rsrc__vgpr_voffset__sgpr_soffset_zext(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i16__vgpr_rsrc__vgpr_voffset__sgpr_soffset_zext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1
+; GFX12-NEXT:    s_mov_b32 s2, exec_lo
+; GFX12-NEXT:  .LBB6_1: ; =>This Inner Loop Header: Depth=1
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_readfirstlane_b32 s4, v5
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_readfirstlane_b32 s5, v6
+; GFX12-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX12-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX12-NEXT:    s_wait_alu 0xf1ff
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
+; GFX12-NEXT:    v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
+; GFX12-NEXT:    s_and_b32 s1, vcc_lo, s1
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    s_and_saveexec_b32 s1, s1
+; GFX12-NEXT:    buffer_load_u16 v6, v4, s[4:7], s0 offen
+; GFX12-NEXT:    ; implicit-def: $vgpr5
+; GFX12-NEXT:    ; implicit-def: $vgpr4
+; GFX12-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX12-NEXT:    s_xor_b32 exec_lo, exec_lo, s1
+; GFX12-NEXT:    s_cbranch_execnz .LBB6_1
+; GFX12-NEXT:  ; %bb.2:
+; GFX12-NEXT:    s_mov_b32 exec_lo, s2
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_mov_b32_e32 v0, v6
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %zext = zext i16 %val to i32
+  %cast = bitcast i32 %zext to float
+  ret float %cast
+}
+
+define amdgpu_ps float @raw_buffer_load_i16__vgpr_rsrc__vgpr_voffset__sgpr_soffset_sext(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
+; GFX12-LABEL: raw_buffer_load_i16__vgpr_rsrc__vgpr_voffset__sgpr_soffset_sext:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1
+; GFX12-NEXT:    s_mov_b32 s2, exec_lo
+; GFX12-NEXT:  .LBB7_1: ; =>This Inner Loop Header: Depth=1
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_readfirstlane_b32 s4, v5
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_readfirstlane_b32 s5, v6
+; GFX12-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX12-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX12-NEXT:    s_wait_alu 0xf1ff
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
+; GFX12-NEXT:    v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
+; GFX12-NEXT:    s_and_b32 s1, vcc_lo, s1
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    s_and_saveexec_b32 s1, s1
+; GFX12-NEXT:    buffer_load_i16 v6, v4, s[4:7], s0 offen
+; GFX12-NEXT:    ; implicit-def: $vgpr5
+; GFX12-NEXT:    ; implicit-def: $vgpr4
+; GFX12-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX12-NEXT:    s_xor_b32 exec_lo, exec_lo, s1
+; GFX12-NEXT:    s_cbranch_execnz .LBB7_1
+; GFX12-NEXT:  ; %bb.2:
+; GFX12-NEXT:    s_mov_b32 exec_lo, s2
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_mov_b32_e32 v0, v6
+; GFX12-NEXT:    ; return to shader part epilog
+  %val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
+  %sext = sext i16 %val to i32
+  %cast = bitcast i32 %sext to float
+  ret float %cast
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
index 7003bb1a09eae..6fb4037ef7278 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
 ; FIXME: Test with SI when argument lowering not broken for f16
 
 ; Natural mapping
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
index 89c3a41eda29c..53206b61be5d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
 ; FIXME: Test with SI when argument lowering not broken for f16
 
 ; Natural mapping
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
index dbef90f6c9ff9..73b549d0ed3e0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s
 
 ; Natural mapping
 define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
index 4ae456d47ea4f..61d839d291983 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
 
 ; Natural mapping
 define amdgpu_ps float @struct_ptr_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

@mssefat mssefat force-pushed the globalisel-regbanklegalize-buffer-load-byte-short branch from 4027426 to 32bfe52 Compare November 13, 2025 19:50
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mssefat commented Nov 17, 2025

Hi @petar-avramovic , could you please review as well? Thank you.

petar-avramovic
petar-avramovic reviewed Nov 18, 2025
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Need to add a few UniInVgpr tests (have load used by instruction that has salu version, for example add)

@mssefat mssefat force-pushed the globalisel-regbanklegalize-buffer-load-byte-short branch from 32bfe52 to bd7e0c7 Compare November 24, 2025 18:57
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mssefat commented Nov 24, 2025

I have moved the tests I initially added to raw.buffer.load.ll into a new file [buffer-load-byte-short.ll], which now contains all the suggested uniform and divergent tests.

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edited
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🐧 Linux x64 Test Results

  • 186541 tests passed
  • 4881 tests skipped

@mssefat mssefat force-pushed the globalisel-regbanklegalize-buffer-load-byte-short branch from bd7e0c7 to 4dfc057 Compare November 24, 2025 19:47
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Small nit for title since there is no G_AMDGPU_BUFFER_LOAD_BYTE_AND_SHORT, can write "buffer_load byte and short"

@mssefat mssefat changed the title [AMDGPU][GlobalISel] Add register bank legalization for G_AMDGPU_BUFFER_LOAD_BYTE_AND_SHORT [AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short Nov 25, 2025
@mssefat mssefat merged commit 4dbd16b into llvm:main Dec 12, 2025
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llvm-ci commented Dec 12, 2025

LLVM Buildbot has detected a new failure on builder ml-opt-devrel-x86-64 running on ml-opt-devrel-x86-64-b1 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/175/builds/30288

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
/b/ml-opt-devrel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll | /b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX12 /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# executed command: /b/ml-opt-devrel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200
# executed command: /b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX12 /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# .---command stderr------------
# | /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:160:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:757:28: note: scanning from here
# |  v_readfirstlane_b32 s7, v3
# |                            ^
# | <stdin>:758:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:192:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:864:23: note: scanning from here
# |  s_mov_b32 s7, exec_lo
# |                       ^
# | <stdin>:865:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:223:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:970:28: note: scanning from here
# |  v_readfirstlane_b32 s9, v5
# |                            ^
# | <stdin>:971:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | 
# | Input file: <stdin>
# | Check file: /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |             .
# |             .
# |             .
# |           752: .LBB8_1: ; =>This Inner Loop Header: Depth=1 
# |           753:  v_readfirstlane_b32 s4, v0 
...

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llvm-ci commented Dec 12, 2025

LLVM Buildbot has detected a new failure on builder ml-opt-rel-x86-64 running on ml-opt-rel-x86-64-b1 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/30321

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
/b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll | /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX12 /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# executed command: /b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200
# executed command: /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX12 /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# .---command stderr------------
# | /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:160:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:757:28: note: scanning from here
# |  v_readfirstlane_b32 s7, v3
# |                            ^
# | <stdin>:758:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:192:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:864:23: note: scanning from here
# |  s_mov_b32 s7, exec_lo
# |                       ^
# | <stdin>:865:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:223:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:970:28: note: scanning from here
# |  v_readfirstlane_b32 s9, v5
# |                            ^
# | <stdin>:971:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | 
# | Input file: <stdin>
# | Check file: /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |             .
# |             .
# |             .
# |           752: .LBB8_1: ; =>This Inner Loop Header: Depth=1 
# |           753:  v_readfirstlane_b32 s4, v0 
...

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llvm-ci commented Dec 12, 2025

LLVM Buildbot has detected a new failure on builder ml-opt-dev-x86-64 running on ml-opt-dev-x86-64-b2 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/137/builds/30567

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
/b/ml-opt-dev-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll | /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck --check-prefix=GFX12 /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# executed command: /b/ml-opt-dev-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200
# executed command: /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck --check-prefix=GFX12 /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# .---command stderr------------
# | /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:160:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:757:28: note: scanning from here
# |  v_readfirstlane_b32 s7, v3
# |                            ^
# | <stdin>:758:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:192:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:864:23: note: scanning from here
# |  s_mov_b32 s7, exec_lo
# |                       ^
# | <stdin>:865:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:223:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:970:28: note: scanning from here
# |  v_readfirstlane_b32 s9, v5
# |                            ^
# | <stdin>:971:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | 
# | Input file: <stdin>
# | Check file: /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |             .
# |             .
# |             .
# |           752: .LBB8_1: ; =>This Inner Loop Header: Depth=1 
# |           753:  v_readfirstlane_b32 s4, v0 
...

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llvm-ci commented Dec 12, 2025

LLVM Buildbot has detected a new failure on builder lld-x86_64-ubuntu-fast running on as-builder-4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/33/builds/27940

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll | /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/FileCheck --check-prefix=GFX12 /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# executed command: /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200
# executed command: /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/FileCheck --check-prefix=GFX12 /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# .---command stderr------------
# | /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:160:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:757:28: note: scanning from here
# |  v_readfirstlane_b32 s7, v3
# |                            ^
# | <stdin>:758:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:192:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:864:23: note: scanning from here
# |  s_mov_b32 s7, exec_lo
# |                       ^
# | <stdin>:865:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:223:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:970:28: note: scanning from here
# |  v_readfirstlane_b32 s9, v5
# |                            ^
# | <stdin>:971:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | 
# | Input file: <stdin>
# | Check file: /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |             .
# |             .
# |             .
# |           752: .LBB8_1: ; =>This Inner Loop Header: Depth=1 
# |           753:  v_readfirstlane_b32 s4, v0 
...

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llvm-ci commented Dec 12, 2025

LLVM Buildbot has detected a new failure on builder openmp-offload-amdgpu-runtime-2 running on rocm-worker-hw-02 while building llvm at step 8 "Add check check-llvm".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/10/builds/18979

Here is the relevant piece of the build log for the reference 
Step 8 (Add check check-llvm) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
/home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll | /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.build/bin/FileCheck --check-prefix=GFX12 /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# executed command: /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.build/bin/llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200
# note: command had no output on stdout or stderr
# executed command: /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.build/bin/FileCheck --check-prefix=GFX12 /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# .---command stderr------------
# | /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:160:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:757:28: note: scanning from here
# |  v_readfirstlane_b32 s7, v3
# |                            ^
# | <stdin>:758:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:192:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:864:23: note: scanning from here
# |  s_mov_b32 s7, exec_lo
# |                       ^
# | <stdin>:865:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll:223:15: error: GFX12-NEXT: expected string not found in input
# | ; GFX12-NEXT: s_wait_alu 0xf1ff
# |               ^
# | <stdin>:970:28: note: scanning from here
# |  v_readfirstlane_b32 s9, v5
# |                            ^
# | <stdin>:971:2: note: possible intended match here
# |  s_wait_alu depctr_va_sdst(0)
# |  ^
# | 
# | Input file: <stdin>
# | Check file: /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |             .
# |             .
# |             .
# |           752: .LBB8_1: ; =>This Inner Loop Header: Depth=1 
...

@ginsbach ginsbach mentioned this pull request Dec 12, 2025
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ginsbach commented Dec 12, 2025

I'm seeing test failures in LLVM.CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll on my entirely unrelated PR: #171524 (comment)

boomanaiden154 added a commit that referenced this pull request Dec 12, 2025
@boomanaiden154
Revert "[AMDGPU][GlobalISel] Add register bank legalization for buffe…
b8816a4 
…r_load byte and short (#167798)"

This reverts commit 4dbd16b.

This was causing buildbot failures, including on premerge when running
check-llvm.

https://lab.llvm.org/buildbot/#/builders/185/builds/30323
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boomanaiden154 commented Dec 12, 2025

I've revert this in b8816a4 due to the breakage and the seeming lack of a forward fix in the last ~30 minutes. Sorry for the inconvenince.

mssefat added a commit to mssefat/llvm-project that referenced this pull request Dec 12, 2025
@mssefat
Revert "Revert "[AMDGPU][GlobalISel] Add register bank legalization f…
19e3c5a 
…or buffer_load byte and short (llvm#167798)""

This reverts commit b8816a4.
@mssefat mssefat mentioned this pull request Dec 12, 2025
Merged
mssefat added a commit that referenced this pull request Dec 12, 2025
@mssefat
[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffe…
f3c1645 
…r_load byte and short (#172065)

This patch adds register bank legalization support for buffer load byte
and short operations in the AMDGPU GlobalISel pipeline.

This is a re-land of #167798. I have fixed the failing test
/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
anonymouspc pushed a commit to anonymouspc/llvm that referenced this pull request Dec 15, 2025
@mssefat @anonymouspc
[AMDGPU][GlobalISel] Add register bank legalization for buffer_load b…
eb9f804 
…yte and short (llvm#167798)

This patch adds register bank legalization support for buffer load byte
and short operations in the AMDGPU GlobalISel pipeline.
anonymouspc pushed a commit to anonymouspc/llvm that referenced this pull request Dec 15, 2025
@boomanaiden154 @anonymouspc
Revert "[AMDGPU][GlobalISel] Add register bank legalization for buffe…
e8e32c3 
…r_load byte and short (llvm#167798)"

This reverts commit 4dbd16b.

This was causing buildbot failures, including on premerge when running
check-llvm.

https://lab.llvm.org/buildbot/#/builders/185/builds/30323
anonymouspc pushed a commit to anonymouspc/llvm that referenced this pull request Dec 15, 2025
@mssefat @anonymouspc
[Reland][AMDGPU][GlobalISel] Add register bank legalization for buffe…
3742408 
…r_load byte and short (llvm#172065)

This patch adds register bank legalization support for buffer load byte
and short operations in the AMDGPU GlobalISel pipeline.

This is a re-land of llvm#167798. I have fixed the failing test
/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
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@petar-avramovic petar-avramovic petar-avramovic approved these changes

@arsenm arsenm Awaiting requested review from arsenm

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@mssefat @llvmbot @llvm-ci @ginsbach @boomanaiden154 @arsenm @petar-avramovic