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[ADT] Make use of subsetOf and anyCommon methods of BitVector (NFC) #170876

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[ADT] Make use of subsetOf and anyCommon methods of BitVector (NFC) #170876

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5 changes: 2 additions & 3 deletions bolt/include/bolt/Passes/LivenessAnalysis.h
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Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,9 @@ class LivenessAnalysis : public DataflowAnalysis<LivenessAnalysis, BitVector,
virtual ~LivenessAnalysis();

bool isAlive(ProgramPoint PP, MCPhysReg Reg) const {
BitVector BV = (*this->getStateAt(PP));
const BitVector &BV = *this->getStateAt(PP);
const BitVector &RegAliases = BC.MIB->getAliases(Reg);
BV &= RegAliases;
return BV.any();
return BV.anyCommon(RegAliases);
}

void run() { Parent::run(); }
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3 changes: 1 addition & 2 deletions bolt/include/bolt/Passes/ReachingDefOrUse.h
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Expand Up @@ -133,8 +133,7 @@ class ReachingDefOrUse
RA.getInstClobberList(Point, Regs);
else
RA.getInstUsedRegsList(Point, Regs, false);
Regs &= this->BC.MIB->getAliases(*TrackingReg);
if (Regs.any())
if (Regs.anyCommon(this->BC.MIB->getAliases(*TrackingReg)))
Next.set(this->ExprToIdx[&Point]);
}
}
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8 changes: 2 additions & 6 deletions bolt/lib/Passes/RegReAssign.cpp
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Expand Up @@ -316,18 +316,14 @@ void RegReAssign::aggressivePassOverFunction(BinaryFunction &Function) {
break;
}

BitVector AnyAliasAlive = AliveAtStart;
AnyAliasAlive &= BC.MIB->getAliases(ClassicReg);
if (AnyAliasAlive.any()) {
if (AliveAtStart.anyCommon(BC.MIB->getAliases(ClassicReg))) {
LLVM_DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg)
<< " with " << BC.MRI->getName(ExtReg)
<< " because classic reg is alive\n");
--End;
continue;
}
AnyAliasAlive = AliveAtStart;
AnyAliasAlive &= BC.MIB->getAliases(ExtReg);
if (AnyAliasAlive.any()) {
if (AliveAtStart.anyCommon(BC.MIB->getAliases(ExtReg))) {
LLVM_DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg)
<< " with " << BC.MRI->getName(ExtReg)
<< " because extended reg is alive\n");
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10 changes: 4 additions & 6 deletions bolt/lib/Passes/ShrinkWrapping.cpp
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Expand Up @@ -1100,19 +1100,17 @@ SmallVector<ProgramPoint, 4> ShrinkWrapping::fixPopsPlacements(
bool Found = false;
if (SPT.getStateAt(ProgramPoint::getLastPointAt(*BB))->first ==
SaveOffset) {
BitVector BV = *RI.getStateAt(ProgramPoint::getLastPointAt(*BB));
BV &= UsesByReg[CSR];
if (!BV.any()) {
const BitVector &BV = *RI.getStateAt(ProgramPoint::getLastPointAt(*BB));
if (!BV.anyCommon(UsesByReg[CSR])) {
Found = true;
PP = BB;
continue;
}
}
for (MCInst &Inst : llvm::reverse(*BB)) {
if (SPT.getStateBefore(Inst)->first == SaveOffset) {
BitVector BV = *RI.getStateAt(Inst);
BV &= UsesByReg[CSR];
if (!BV.any()) {
const BitVector &BV = *RI.getStateAt(Inst);
if (!BV.anyCommon(UsesByReg[CSR])) {
Found = true;
PP = &Inst;
break;
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3 changes: 1 addition & 2 deletions bolt/lib/Passes/StackAvailableExpressions.cpp
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Expand Up @@ -103,8 +103,7 @@ bool StackAvailableExpressions::doesXKillsY(const MCInst *X, const MCInst *Y) {
else
RA.getInstClobberList(*Y, YClobbers);

XClobbers &= YClobbers;
return XClobbers.any();
return XClobbers.anyCommon(YClobbers);
}

BitVector StackAvailableExpressions::computeNext(const MCInst &Point,
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8 changes: 4 additions & 4 deletions bolt/lib/Passes/TailDuplication.cpp
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Expand Up @@ -97,8 +97,8 @@ bool TailDuplication::regIsPossiblyOverwritten(const MCInst &Inst, unsigned Reg,
getCallerSavedRegs(Inst, WrittenRegs, BC);
if (BC.MIB->isRep(Inst))
BC.MIB->getRepRegs(WrittenRegs);
WrittenRegs &= BC.MIB->getAliases(Reg, false);
return WrittenRegs.any();
const BitVector &AllAliases = BC.MIB->getAliases(Reg, false);
return WrittenRegs.anyCommon(AllAliases);
}

bool TailDuplication::regIsDefinitelyOverwritten(const MCInst &Inst,
Expand All @@ -117,8 +117,8 @@ bool TailDuplication::regIsUsed(const MCInst &Inst, unsigned Reg,
BinaryContext &BC) const {
BitVector SrcRegs = BitVector(BC.MRI->getNumRegs(), false);
BC.MIB->getSrcRegs(Inst, SrcRegs);
SrcRegs &= BC.MIB->getAliases(Reg, true);
return SrcRegs.any();
const BitVector &SmallerAliases = BC.MIB->getAliases(Reg, true);
return SrcRegs.anyCommon(SmallerAliases);
}

bool TailDuplication::isOverwrittenBeforeUsed(BinaryBasicBlock &StartBB,
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6 changes: 2 additions & 4 deletions llvm/lib/CodeGen/RDFRegisters.cpp
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Expand Up @@ -287,10 +287,8 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
}

bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
if (RR.isMask()) {
BitVector T(PRI.getMaskUnits(RR));
return T.reset(Units).none();
}
if (RR.isMask())
return PRI.getMaskUnits(RR).subsetOf(Units);

for (MCRegUnitMaskIterator U(RR.asMCReg(), &PRI.getTRI()); U.isValid(); ++U) {
auto [Unit, LaneMask] = *U;
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6 changes: 2 additions & 4 deletions llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
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Expand Up @@ -274,11 +274,9 @@ static Error randomizeMCOperand(const LLVMState &State,
break;
case MCOI::OperandType::OPERAND_REGISTER: {
assert(Op.isReg());
auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
const BitVector &AllowedRegs = Op.getRegisterAliasing().sourceBits();
assert(AllowedRegs.size() == ForbiddenRegs.size());
for (auto I : ForbiddenRegs.set_bits())
AllowedRegs.reset(I);
if (!AllowedRegs.any())
if (AllowedRegs.subsetOf(ForbiddenRegs))
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Contributor Author

@atrosinenko atrosinenko Dec 11, 2025

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Sorry, just spotted that the change in this line is incorrect due to AllowedRegs being later used as

  AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));

return make_error<Failure>(
Twine("no available registers:\ncandidates:\n")
.concat(debugString(State.getRegInfo(),
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