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[X86] Use vectorized i256 bit counts when we know the source originated from the vector unit #171589

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Merged
RKSimon merged 3 commits into from
Dec 10, 2025
Merged

[X86] Use vectorized i256 bit counts when we know the source originated from the vector unit #171589

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ceb9dc3
[X86] Use vectorized i256 bit counts when we know the source originat…
RKSimon Dec 10, 2025
ba15ee4
Rename mayFoldToVector -> mayFoldIntoVector
RKSimon Dec 10, 2025
21e5269
Merge branch 'main' into x86-cntbits-from-vector
RKSimon Dec 10, 2025
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11 changes: 10 additions & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2846,6 +2846,15 @@ bool X86::mayFoldIntoZeroExtend(SDValue Op) {
return false;
}

// Return true if its cheap to bitcast this to a vector type.
static bool mayFoldIntoVector(SDValue Op, const X86Subtarget &Subtarget) {
if (peekThroughBitcasts(Op).getValueType().isVector())
return true;
if (isa<ConstantSDNode>(Op) || isa<ConstantFPSDNode>(Op))
return true;
return X86::mayFoldLoad(Op, Subtarget);
}

static bool isLogicOp(unsigned Opcode) {
// TODO: Add support for X86ISD::FAND/FOR/FXOR/FANDN with test coverage.
return ISD::isBitwiseLogicOp(Opcode) || X86ISD::ANDNP == Opcode;
Expand Down Expand Up @@ -33958,7 +33967,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
EVT VT = N->getValueType(0);
assert(Subtarget.hasCDI() && "AVX512CD required");
assert((VT == MVT::i256 || VT == MVT::i512) && "Unexpected VT!");
if (VT == MVT::i256 && !X86::mayFoldLoad(N0, Subtarget))
if (VT == MVT::i256 && !mayFoldIntoVector(N0, Subtarget))
return;

unsigned SizeInBits = VT.getSizeInBits();
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