Revert "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) #171787

jmmartinez · 2025-12-11T09:39:58Z

# | *** Bad machine code: Illegal virtual register for instruction ***
# | - function:    insert_dyn_i32_6
# | - basic block: %bb.1  (0x55fccb64ff30)
# | - instruction: %18:vreg_192 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 %26:vreg_192(tied-def 0), %15:vgpr_32, 3, implicit $m0, implicit $exec
# | - operand 0:   %18:vreg_192
# | Expected a VReg_256 register, but got a VReg_192 register

This reverts commit 15df9e7.

…0323)" This reverts commit 15df9e7.

llvmbot · 2025-12-11T09:40:32Z

@llvm/pr-subscribers-backend-amdgpu

Author: Juan Manuel Martinez Caamaño (jmmartinez)

Changes

Step 7 (test-check-all) failure: Test just built components: check-all completed (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/insert_vector_dynelt.ll' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
/home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/build/bin/llc -mtriple=amdgcn -mcpu=fiji &lt; /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/llvm-project/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll | /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/build/bin/FileCheck -enable-var-scope -check-prefixes=GCN /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/llvm-project/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
# executed command: /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/build/bin/llc -mtriple=amdgcn -mcpu=fiji
# executed command: /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/build/bin/FileCheck -enable-var-scope -check-prefixes=GCN /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/llvm-project/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
# RUN: at line 3
/home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/build/bin/llc -O0 -mtriple=amdgcn -mcpu=fiji &lt; /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/llvm-project/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll | /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/build/bin/FileCheck --check-prefixes=GCN-O0 /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/llvm-project/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
# executed command: /home/buildbot/worker/as-builder-4/ramdisk/expensive-checks/build/bin/llc -O0 -mtriple=amdgcn -mcpu=fiji
# .---command stderr------------
# |
# | # After Instruction Selection
# | # Machine code for function insert_dyn_i32_6: IsSSA, TracksLiveness
# | Function Live Ins: $sgpr16 in %8, $sgpr17 in %9, $sgpr18 in %10, $sgpr19 in %11, $sgpr20 in %12, $sgpr21 in %13, $vgpr0 in %14, $vgpr1 in %15
# |
# | bb.0 (%ir-block.0):
# |   successors: %bb.1(0x80000000); %bb.1(100.00%)
# |   liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $vgpr0, $vgpr1
# |   %15:vgpr_32 = COPY $vgpr1
# |   %14:vgpr_32 = COPY $vgpr0
# |   %13:sgpr_32 = COPY $sgpr21
# |   %12:sgpr_32 = COPY $sgpr20
# |   %11:sgpr_32 = COPY $sgpr19
# |   %10:sgpr_32 = COPY $sgpr18
# |   %9:sgpr_32 = COPY $sgpr17
# |   %8:sgpr_32 = COPY $sgpr16
# |   %17:sgpr_192 = REG_SEQUENCE %8:sgpr_32, %subreg.sub0, %9:sgpr_32, %subreg.sub1, %10:sgpr_32, %subreg.sub2, %11:sgpr_32, %subreg.sub3, %12:sgpr_32, %subreg.sub4, %13:sgpr_32, %subreg.sub5
# |   %16:sgpr_192 = COPY %17:sgpr_192
# |   %19:vreg_192 = COPY %17:sgpr_192
# |   %28:sreg_64_xexec = IMPLICIT_DEF
# |   %27:sreg_64_xexec = S_MOV_B64 $exec
# |
# | bb.1:
# | ; predecessors: %bb.1, %bb.0
# |   successors: %bb.1(0x40000000), %bb.3(0x40000000); %bb.1(50.00%), %bb.3(50.00%)
# |
# |   %26:vreg_192 = PHI %19:vreg_192, %bb.0, %18:vreg_192, %bb.1
# |   %29:sreg_64 = PHI %28:sreg_64_xexec, %bb.0, %30:sreg_64, %bb.1
# |   %31:sreg_32_xm0 = V_READFIRSTLANE_B32 %14:vgpr_32, implicit $exec
# |   %32:sreg_64 = V_CMP_EQ_U32_e64 %31:sreg_32_xm0, %14:vgpr_32, implicit $exec
# |   %30:sreg_64 = S_AND_SAVEEXEC_B64 killed %32:sreg_64, implicit-def $exec, implicit-def $scc, implicit $exec
# |   $m0 = COPY killed %31:sreg_32_xm0
# |   %18:vreg_192 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 %26:vreg_192(tied-def 0), %15:vgpr_32, 3, implicit $m0, implicit $exec
# |   $exec = S_XOR_B64_term $exec, %30:sreg_64, implicit-def $scc
# |   S_CBRANCH_EXECNZ %bb.1, implicit $exec
# |
# | bb.3:

This reverts commit 15df9e7.

Patch is 485.28 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171787.diff

4 Files Affected:

(modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (-8)
(modified) llvm/lib/Target/AMDGPU/SIInstructions.td (-16)
(modified) llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll (-3310)
(modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (-5963)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 76bbb30b85a78..4651d7d9d3adf 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6304,11 +6304,7 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   }
   case AMDGPU::SI_INDIRECT_SRC_V1:
   case AMDGPU::SI_INDIRECT_SRC_V2:
-  case AMDGPU::SI_INDIRECT_SRC_V3:
   case AMDGPU::SI_INDIRECT_SRC_V4:
-  case AMDGPU::SI_INDIRECT_SRC_V5:
-  case AMDGPU::SI_INDIRECT_SRC_V6:
-  case AMDGPU::SI_INDIRECT_SRC_V7:
   case AMDGPU::SI_INDIRECT_SRC_V8:
   case AMDGPU::SI_INDIRECT_SRC_V9:
   case AMDGPU::SI_INDIRECT_SRC_V10:
@@ -6319,11 +6315,7 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return emitIndirectSrc(MI, *BB, *getSubtarget());
   case AMDGPU::SI_INDIRECT_DST_V1:
   case AMDGPU::SI_INDIRECT_DST_V2:
-  case AMDGPU::SI_INDIRECT_DST_V3:
   case AMDGPU::SI_INDIRECT_DST_V4:
-  case AMDGPU::SI_INDIRECT_DST_V5:
-  case AMDGPU::SI_INDIRECT_DST_V6:
-  case AMDGPU::SI_INDIRECT_DST_V7:
   case AMDGPU::SI_INDIRECT_DST_V8:
   case AMDGPU::SI_INDIRECT_DST_V9:
   case AMDGPU::SI_INDIRECT_DST_V10:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 643b2463344e5..984d1a4db4cd6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -969,11 +969,7 @@ class SI_INDIRECT_DST<RegisterClass rc> : VPseudoInstSI <
 
 def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>;
 def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>;
-def SI_INDIRECT_SRC_V3 : SI_INDIRECT_SRC<VReg_96>;
 def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>;
-def SI_INDIRECT_SRC_V5 : SI_INDIRECT_SRC<VReg_160>;
-def SI_INDIRECT_SRC_V6 : SI_INDIRECT_SRC<VReg_192>;
-def SI_INDIRECT_SRC_V7 : SI_INDIRECT_SRC<VReg_224>;
 def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>;
 def SI_INDIRECT_SRC_V9 : SI_INDIRECT_SRC<VReg_288>;
 def SI_INDIRECT_SRC_V10 : SI_INDIRECT_SRC<VReg_320>;
@@ -984,11 +980,7 @@ def SI_INDIRECT_SRC_V32 : SI_INDIRECT_SRC<VReg_1024>;
 
 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
-def SI_INDIRECT_DST_V3 : SI_INDIRECT_DST<VReg_96>;
 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
-def SI_INDIRECT_DST_V5 : SI_INDIRECT_DST<VReg_160>;
-def SI_INDIRECT_DST_V6 : SI_INDIRECT_DST<VReg_192>;
-def SI_INDIRECT_DST_V7 : SI_INDIRECT_DST<VReg_224>;
 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
 def SI_INDIRECT_DST_V9 : SI_INDIRECT_DST<VReg_288>;
 def SI_INDIRECT_DST_V10 : SI_INDIRECT_DST<VReg_320>;
@@ -2787,11 +2779,7 @@ multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
 }
 
 defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
-defm : SI_INDIRECT_Pattern<v3f32, f32, "V3">;
 defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
-defm : SI_INDIRECT_Pattern<v5f32, f32, "V5">;
-defm : SI_INDIRECT_Pattern<v6f32, f32, "V6">;
-defm : SI_INDIRECT_Pattern<v7f32, f32, "V7">;
 defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
 defm : SI_INDIRECT_Pattern <v9f32, f32, "V9">;
 defm : SI_INDIRECT_Pattern <v10f32, f32, "V10">;
@@ -2801,11 +2789,7 @@ defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
 defm : SI_INDIRECT_Pattern <v32f32, f32, "V32">;
 
 defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">;
-defm : SI_INDIRECT_Pattern<v3i32, i32, "V3">;
 defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">;
-defm : SI_INDIRECT_Pattern<v5i32, i32, "V5">;
-defm : SI_INDIRECT_Pattern<v6i32, i32, "V6">;
-defm : SI_INDIRECT_Pattern<v7i32, i32, "V7">;
 defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
 defm : SI_INDIRECT_Pattern <v9i32, i32, "V9">;
 defm : SI_INDIRECT_Pattern <v10i32, i32, "V10">;
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index 4b340f308d5f6..c69b0cce3d208 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN %s
-; RUN: llc -O0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefixes=GCN-O0 %s
 
 define amdgpu_kernel void @float4_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-LABEL: float4_extelt:
@@ -21,30 +20,6 @@ define amdgpu_kernel void @float4_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v1, s1
 ; GCN-NEXT:    flat_store_dword v[0:1], v2
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: float4_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s2, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s3, 4.0
-; GCN-O0-NEXT:    s_mov_b32 s4, 2.0
-; GCN-O0-NEXT:    s_mov_b32 s5, 1.0
-; GCN-O0-NEXT:    s_mov_b32 s6, 0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v4, s3
-; GCN-O0-NEXT:    ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, v6
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, v5
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, v4
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v2, v0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-O0-NEXT:    flat_store_dword v[0:1], v2
-; GCN-O0-NEXT:    s_endpgm
 entry:
   %ext = extractelement <4 x float> <float 0.0, float 1.0, float 2.0, float 4.0>, i32 %sel
   store float %ext, ptr addrspace(1) %out
@@ -68,30 +43,6 @@ define amdgpu_kernel void @int4_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v2, s2
 ; GCN-NEXT:    flat_store_dword v[0:1], v2
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: int4_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s2, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s3, 4
-; GCN-O0-NEXT:    s_mov_b32 s4, 2
-; GCN-O0-NEXT:    s_mov_b32 s5, 1
-; GCN-O0-NEXT:    s_mov_b32 s6, 0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v4, s3
-; GCN-O0-NEXT:    ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3 killed $exec
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, v6
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, v5
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, v4
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v2, v0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-O0-NEXT:    flat_store_dword v[0:1], v2
-; GCN-O0-NEXT:    s_endpgm
 entry:
   %ext = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 4>, i32 %sel
   store i32 %ext, ptr addrspace(1) %out
@@ -121,72 +72,6 @@ define amdgpu_kernel void @double4_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v2, s0
 ; GCN-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: double4_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s2, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x40100a3d
-; GCN-O0-NEXT:    s_mov_b32 s4, 0x70a3d70a
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s3
-; GCN-O0-NEXT:    s_mov_b32 s3, s5
-; GCN-O0-NEXT:    s_mov_b32 s12, s4
-; GCN-O0-NEXT:    s_mov_b32 s6, 0x4000147a
-; GCN-O0-NEXT:    s_mov_b32 s4, 0xe147ae14
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s6
-; GCN-O0-NEXT:    s_mov_b32 s13, s5
-; GCN-O0-NEXT:    s_mov_b32 s14, s4
-; GCN-O0-NEXT:    s_mov_b32 s6, 0x3ff028f5
-; GCN-O0-NEXT:    s_mov_b32 s4, 0xc28f5c29
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s6
-; GCN-O0-NEXT:    s_mov_b32 s15, s5
-; GCN-O0-NEXT:    s_mov_b32 s16, s4
-; GCN-O0-NEXT:    s_mov_b32 s6, 0x3f847ae1
-; GCN-O0-NEXT:    s_mov_b32 s4, 0x47ae147b
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s6
-; GCN-O0-NEXT:    s_mov_b32 s17, s5
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 killed $sgpr4_sgpr5
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
-; GCN-O0-NEXT:    s_mov_b32 s5, s17
-; GCN-O0-NEXT:    s_mov_b32 s6, s16
-; GCN-O0-NEXT:    s_mov_b32 s7, s15
-; GCN-O0-NEXT:    s_mov_b32 s8, s14
-; GCN-O0-NEXT:    s_mov_b32 s9, s13
-; GCN-O0-NEXT:    s_mov_b32 s10, s12
-; GCN-O0-NEXT:    s_mov_b32 s11, s3
-; GCN-O0-NEXT:    s_mov_b32 s3, 1
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_lshl_b32 s2, s2, s3
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT:    v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT:    v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT:    v_mov_b32_e32 v6, s10
-; GCN-O0-NEXT:    v_mov_b32_e32 v7, s11
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v0, v1
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v4, s7
-; GCN-O0-NEXT:    v_mov_b32_e32 v5, s8
-; GCN-O0-NEXT:    v_mov_b32_e32 v6, s9
-; GCN-O0-NEXT:    v_mov_b32_e32 v7, s10
-; GCN-O0-NEXT:    v_mov_b32_e32 v8, s11
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v2, v1
-; GCN-O0-NEXT:    ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, v0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-O0-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; GCN-O0-NEXT:    s_endpgm
 entry:
   %ext = extractelement <4 x double> <double 0.01, double 1.01, double 2.01, double 4.01>, i32 %sel
   store double %ext, ptr addrspace(1) %out
@@ -224,113 +109,6 @@ define amdgpu_kernel void @double5_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v2, s0
 ; GCN-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: double5_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s2, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x40140a3d
-; GCN-O0-NEXT:    s_mov_b32 s4, 0x70a3d70a
-; GCN-O0-NEXT:    s_mov_b32 s6, s4
-; GCN-O0-NEXT:    s_mov_b32 s7, s3
-; GCN-O0-NEXT:    s_mov_b32 s25, s7
-; GCN-O0-NEXT:    s_mov_b32 s26, s6
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x40100a3d
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s3
-; GCN-O0-NEXT:    s_mov_b32 s27, s5
-; GCN-O0-NEXT:    s_mov_b32 s28, s4
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x4000147a
-; GCN-O0-NEXT:    s_mov_b32 s4, 0xe147ae14
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s3
-; GCN-O0-NEXT:    s_mov_b32 s29, s5
-; GCN-O0-NEXT:    s_mov_b32 s30, s4
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x3ff028f5
-; GCN-O0-NEXT:    s_mov_b32 s4, 0xc28f5c29
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s3
-; GCN-O0-NEXT:    s_mov_b32 s31, s5
-; GCN-O0-NEXT:    s_mov_b32 s33, s4
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x3f847ae1
-; GCN-O0-NEXT:    s_mov_b32 s4, 0x47ae147b
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s3
-; GCN-O0-NEXT:    s_mov_b32 s34, s5
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 killed $sgpr4_sgpr5
-; GCN-O0-NEXT:    ; implicit-def: $sgpr24
-; GCN-O0-NEXT:    ; implicit-def: $sgpr3
-; GCN-O0-NEXT:    ; implicit-def: $sgpr23
-; GCN-O0-NEXT:    ; implicit-def: $sgpr3
-; GCN-O0-NEXT:    ; implicit-def: $sgpr22
-; GCN-O0-NEXT:    ; implicit-def: $sgpr3
-; GCN-O0-NEXT:    ; implicit-def: $sgpr21
-; GCN-O0-NEXT:    ; implicit-def: $sgpr3
-; GCN-O0-NEXT:    ; implicit-def: $sgpr20
-; GCN-O0-NEXT:    ; implicit-def: $sgpr3
-; GCN-O0-NEXT:    ; implicit-def: $sgpr3
-; GCN-O0-NEXT:    ; implicit-def: $sgpr5
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19
-; GCN-O0-NEXT:    s_mov_b32 s5, s34
-; GCN-O0-NEXT:    s_mov_b32 s6, s33
-; GCN-O0-NEXT:    s_mov_b32 s7, s31
-; GCN-O0-NEXT:    s_mov_b32 s8, s30
-; GCN-O0-NEXT:    s_mov_b32 s9, s29
-; GCN-O0-NEXT:    s_mov_b32 s10, s28
-; GCN-O0-NEXT:    s_mov_b32 s11, s27
-; GCN-O0-NEXT:    s_mov_b32 s12, s26
-; GCN-O0-NEXT:    s_mov_b32 s13, s25
-; GCN-O0-NEXT:    s_mov_b32 s14, s24
-; GCN-O0-NEXT:    s_mov_b32 s15, s23
-; GCN-O0-NEXT:    s_mov_b32 s16, s22
-; GCN-O0-NEXT:    s_mov_b32 s17, s21
-; GCN-O0-NEXT:    s_mov_b32 s18, s20
-; GCN-O0-NEXT:    s_mov_b32 s19, s3
-; GCN-O0-NEXT:    s_mov_b32 s3, 1
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_lshl_b32 s2, s2, s3
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT:    v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT:    v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT:    v_mov_b32_e32 v6, s10
-; GCN-O0-NEXT:    v_mov_b32_e32 v7, s11
-; GCN-O0-NEXT:    v_mov_b32_e32 v8, s12
-; GCN-O0-NEXT:    v_mov_b32_e32 v9, s13
-; GCN-O0-NEXT:    v_mov_b32_e32 v10, s14
-; GCN-O0-NEXT:    v_mov_b32_e32 v11, s15
-; GCN-O0-NEXT:    v_mov_b32_e32 v12, s16
-; GCN-O0-NEXT:    v_mov_b32_e32 v13, s17
-; GCN-O0-NEXT:    v_mov_b32_e32 v14, s18
-; GCN-O0-NEXT:    v_mov_b32_e32 v15, s19
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v0, v1
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v4, s7
-; GCN-O0-NEXT:    v_mov_b32_e32 v5, s8
-; GCN-O0-NEXT:    v_mov_b32_e32 v6, s9
-; GCN-O0-NEXT:    v_mov_b32_e32 v7, s10
-; GCN-O0-NEXT:    v_mov_b32_e32 v8, s11
-; GCN-O0-NEXT:    v_mov_b32_e32 v9, s12
-; GCN-O0-NEXT:    v_mov_b32_e32 v10, s13
-; GCN-O0-NEXT:    v_mov_b32_e32 v11, s14
-; GCN-O0-NEXT:    v_mov_b32_e32 v12, s15
-; GCN-O0-NEXT:    v_mov_b32_e32 v13, s16
-; GCN-O0-NEXT:    v_mov_b32_e32 v14, s17
-; GCN-O0-NEXT:    v_mov_b32_e32 v15, s18
-; GCN-O0-NEXT:    v_mov_b32_e32 v16, s19
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v2, v1
-; GCN-O0-NEXT:    ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, v0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-O0-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; GCN-O0-NEXT:    s_endpgm
 entry:
   %ext = extractelement <5 x double> <double 0.01, double 1.01, double 2.01, double 4.01, double 5.01>, i32 %sel
   store double %ext, ptr addrspace(1) %out
@@ -352,25 +130,6 @@ define amdgpu_kernel void @half4_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v2, s2
 ; GCN-NEXT:    flat_store_short v[0:1], v2
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: half4_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s4, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s5, 0x44004200
-; GCN-O0-NEXT:    s_mov_b32 s0, 0x40003c00
-; GCN-O0-NEXT:    ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
-; GCN-O0-NEXT:    s_mov_b32 s1, s5
-; GCN-O0-NEXT:    s_mov_b32 s5, 4
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_lshl_b32 s4, s4, s5
-; GCN-O0-NEXT:    s_lshr_b64 s[0:1], s[0:1], s4
-; GCN-O0-NEXT:    ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s2
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s3
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s0
-; GCN-O0-NEXT:    flat_store_short v[0:1], v2
-; GCN-O0-NEXT:    s_endpgm
 entry:
   %ext = extractelement <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, i32 %sel
   store half %ext, ptr addrspace(1) %out
@@ -390,24 +149,6 @@ define amdgpu_kernel void @float2_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v1, s1
 ; GCN-NEXT:    flat_store_dword v[0:1], v2
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: float2_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s2, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s3, 1.0
-; GCN-O0-NEXT:    s_mov_b32 s4, 0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s3
-; GCN-O0-NEXT:    ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, v2
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v2, v0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-O0-NEXT:    flat_store_dword v[0:1], v2
-; GCN-O0-NEXT:    s_endpgm
 entry:
   %ext = extractelement <2 x float> <float 0.0, float 1.0>, i32 %sel
   store float %ext, ptr addrspace(1) %out
@@ -431,48 +172,6 @@ define amdgpu_kernel void @double2_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v2, s0
 ; GCN-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: double2_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s2, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x3ff028f5
-; GCN-O0-NEXT:    s_mov_b32 s4, 0xc28f5c29
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s3
-; GCN-O0-NEXT:    s_mov_b32 s3, s5
-; GCN-O0-NEXT:    s_mov_b32 s8, s4
-; GCN-O0-NEXT:    s_mov_b32 s6, 0x3f847ae1
-; GCN-O0-NEXT:    s_mov_b32 s4, 0x47ae147b
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GCN-O0-NEXT:    s_mov_b32 s5, s6
-; GCN-O0-NEXT:    s_mov_b32 s9, s5
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 killed $sgpr4_sgpr5
-; GCN-O0-NEXT:    ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7
-; GCN-O0-NEXT:    s_mov_b32 s5, s9
-; GCN-O0-NEXT:    s_mov_b32 s6, s8
-; GCN-O0-NEXT:    s_mov_b32 s7, s3
-; GCN-O0-NEXT:    s_mov_b32 s3, 1
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_lshl_b32 s2, s2, s3
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v0, v1
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s4
-; GCN-O0-NEXT:    v_mov_b32_e32 v2, s5
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v4, s7
-; GCN-O0-NEXT:    s_mov_b32 m0, s2
-; GCN-O0-NEXT:    v_movrels_b32_e32 v2, v1
-; GCN-O0-NEXT:    ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec
-; GCN-O0-NEXT:    v_mov_b32_e32 v3, v0
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-O0-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; GCN-O0-NEXT:    s_endpgm
 entry:
   %ext = extractelement <2 x double> <double 0.01, double 1.01>, i32 %sel
   store double %ext, ptr addrspace(1) %out
@@ -518,60 +217,6 @@ define amdgpu_kernel void @half8_extelt(ptr addrspace(1) %out, i32 %sel) {
 ; GCN-NEXT:    v_mov_b32_e32 v1, s1
 ; GCN-NEXT:    flat_store_short v[0:1], v2
 ; GCN-NEXT:    s_endpgm
-;
-; GCN-O0-LABEL: half8_extelt:
-; GCN-O0:       ; %bb.0: ; %entry
-; GCN-O0-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-O0-NEXT:    s_load_dword s2, s[4:5], 0x2c
-; GCN-O0-NEXT:    s_mov_b32 s3, 1
-; GCN-O0-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-O0-NEXT:    s_cmp_eq_u32 s2, s3
-; GCN-O0-NEXT:    s_cselect_b64 s[4:5], -1, 0
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x4000
-; GCN-O0-NEXT:    s_mov_b32 s6, 0x3c00
-; GCN-O0-NEXT:    v_mov_b32_e32 v0, s6
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s3
-; GCN-O0-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GCN-O0-NEXT:    s_mov_b32 s3, 2
-; GCN-O0-NEXT:    s_cmp_eq_u32 s2, s3
-; GCN-O0-NEXT:    s_cselect_b64 s[4:5], -1, 0
-; GCN-O0-NEXT:    s_mov_b32 s3, 0x4200
-; GCN-O0-NEXT:    v_mov_b32_e32 v1, s3
-; GCN-O0-NEXT:    v_cndmask_b32_e64 v0, v0, v...
[truncated]

Revert "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#17…

4f94941

…0323)" This reverts commit 15df9e7.

llvmbot added the backend:AMDGPU label Dec 11, 2025

jmmartinez mentioned this pull request Dec 11, 2025

[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST #170323

Merged

jmmartinez enabled auto-merge (squash) December 11, 2025 09:56

jmmartinez merged commit c029788 into main Dec 11, 2025
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jmmartinez deleted the users/jmmartinez/revert/fix/extract_insert_vector_dynelt_with_O0 branch December 11, 2025 10:08

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Revert "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) #171787

Revert "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) #171787

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Revert "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) #171787

Revert "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323) #171787

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