[RISCV] Recognize veyron-v1 processor in clang driver.

[mgudim]

Subsequent PRs will add the scheduling model and support for macro fusions.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-clang

Changes

Subsequent PRs will add the scheduling model and support for macro fusions.

---

Full diff: https://github.com/llvm/llvm-project/pull/66703.diff

3 Files Affected:

• (modified) clang/test/Driver/riscv-cpus.c (+25)
• (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2)
• (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+22)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index bd8488d81c0b156..3eaceedce685fc6 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -37,6 +37,31 @@
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
 // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s
+// MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
+// MCPU-VEYRON-V1: "-target-feature" "+m"
+// MCPU-VEYRON-V1: "-target-feature" "+a"
+// MCPU-VEYRON-V1: "-target-feature" "+f"
+// MCPU-VEYRON-V1: "-target-feature" "+d"
+// MCPU-VEYRON-V1: "-target-feature" "+c"
+// MCPU-VEYRON-V1: "-target-feature" "+zicbom"
+// MCPU-VEYRON-V1: "-target-feature" "+zicbop"
+// MCPU-VEYRON-V1: "-target-feature" "+zicboz"
+// MCPU-VEYRON-V1: "-target-feature" "+zicntr"
+// MCPU-VEYRON-V1: "-target-feature" "+zicsr"
+// MCPU-VEYRON-V1: "-target-feature" "+zifencei"
+// MCPU-VEYRON-V1: "-target-feature" "+zihintpause"
+// MCPU-VEYRON-V1: "-target-feature" "+zihpm"
+// MCPU-VEYRON-V1: "-target-feature" "+zba"
+// MCPU-VEYRON-V1: "-target-feature" "+zbb"
+// MCPU-VEYRON-V1: "-target-feature" "+zbc"
+// MCPU-VEYRON-V1: "-target-feature" "+zbs"
+// MCPU-VEYRON-V1: "-target-feature" "+xventanacondops"
+// MCPU-VEYRON-V1: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s
+// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
+
 // Check mtune alias CPU has resolved to the right CPU according XLEN.
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index c44bd6087af4132..a639b0ddde85e5a 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 01291001cd7ca24..402ec20fe39ab1c 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -201,3 +201,25 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
                                               FeatureStdExtM,
                                               FeatureStdExtC],
                                              [TuneNoDefaultUnroll]>;
+
+def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
+                                            NoSchedModel,
+                                            [Feature64Bit,
+                                             FeatureStdExtZifencei,
+                                             FeatureStdExtZicsr,
+                                             FeatureStdExtZicntr,
+                                             FeatureStdExtZihpm,
+                                             FeatureStdExtZihintpause,
+                                             FeatureStdExtM,
+                                             FeatureStdExtA,
+                                             FeatureStdExtF,
+                                             FeatureStdExtD,
+                                             FeatureStdExtC,
+                                             FeatureStdExtZba,
+                                             FeatureStdExtZbb,
+                                             FeatureStdExtZbc,
+                                             FeatureStdExtZbs,
+                                             FeatureStdExtZicbom,
+                                             FeatureStdExtZicbop,
+                                             FeatureStdExtZicboz,
+                                             FeatureVendorXVentanaCondOps]>;

[michaelmaitland]

LGTM.