[PowerPC] Mask constant operands in ValueBit tracking #67653
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ecnelises
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bzEq,
chenzheng1030,
orcguru,
nemanjai,
amy-kwan,
EsmeYi,
lei137 and
stefanp-synopsys
ecnelises
commented
Sep 28, 2023
| ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE64 | ||
| ; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE32 | ||
| ; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE64 | ||
| ; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE32 |
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-mcpu=pwr8 touches another codepath (such instructions are not generated, so only crash on -mcpu=pwr7).
The crash comes from constant shift amounts of srl_parts, which only presents after splitting v2i128 into v1i128 (from the subtraction parts).
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I was going to report the following bug, but since it is already fixed by this change, maybe this even simpler repro would be useful to add as a test since it doesn't involve any vectors: target triple = "powerpc"
define i64 @entry(ptr) {
store i6 0, ptr %0
%2 = load i8, ptr %0
%3 = and i8 %2, 63
%4 = zext i8 %3 to i64
%5 = shl i64 1, %4
ret i64 %5
} |
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Thank you @bzEq for the quick response. Would it be possible to backport this into 18? |
In IR or C code, left/right shift amount larger than value size is undefined behavior. But in practise, backend lowering for srl_parts/sra_parts/shl_parts produces add/sub of shift amounts, thus constant shift amounts might be negative or larger than value size. And the lowering depends on behavior in ISA. PowerPC ISA says, the lowest 7 bits (6 bits if in 32-bit instruction) will be taken, and if the highest among them is 1, result will be zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift amount. This patch emulates the behavior and avoids array overflow in bit permutation's value bits calculator.
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/cherry-pick 292d9e8 |
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Failed to create pull request for issue67653 https://github.com/llvm/llvm-project/actions/runs/7967856697 |
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/cherry-pick 292d9e8 |
llvmbot
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Feb 20, 2024
In IR or C code, shift amount larger than value size is undefined behavior. But in practice, backend lowering for shift_parts produces add/sub of shift amounts, thus constant shift amounts might be negative or larger than value size, which depends on ISA definition. PowerPC ISA says, the lowest 7 bits (6 bits for 32-bit instruction) will be taken, and if the highest among them is 1, result will be zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift amount. This commit emulates the behavior and avoids array overflow in bit permutation's value bits calculator. (cherry picked from commit 292d9e8)
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/pull-request #82301 |
llvmbot
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Feb 20, 2024
In IR or C code, shift amount larger than value size is undefined behavior. But in practice, backend lowering for shift_parts produces add/sub of shift amounts, thus constant shift amounts might be negative or larger than value size, which depends on ISA definition. PowerPC ISA says, the lowest 7 bits (6 bits for 32-bit instruction) will be taken, and if the highest among them is 1, result will be zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift amount. This commit emulates the behavior and avoids array overflow in bit permutation's value bits calculator. (cherry picked from commit 292d9e8)
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In IR or C code, shift amount larger than value size is undefined
behavior. But in practice, backend lowering for shift_parts produces
add/sub of shift amounts, thus constant shift amounts might be
negative or larger than value size, which depends on ISA definition.
PowerPC ISA says, the lowest 7 bits (6 bits for 32-bit instruction)
will be taken, and if the highest among them is 1, result will be
zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift
amount.
This commit emulates the behavior and avoids array overflow in bit
permutation's value bits calculator.
Fixes #59074