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[RISCV] Use TableGen-based macro fusion #72224

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Merged
merged 1 commit into from
Jan 25, 2024
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[RISCV] Use TableGen-based macro fusion #72224

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ set(LLVM_TARGET_DEFINITIONS RISCV.td)
tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
Expand Down Expand Up @@ -43,7 +44,6 @@ add_llvm_target(RISCVCodeGen
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp
RISCVMachineFunctionInfo.cpp
RISCVMacroFusion.cpp
RISCVMergeBaseOffset.cpp
RISCVOptWInstrs.cpp
RISCVPostRAExpandPseudoInsts.cpp
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6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/RISCV.td
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Expand Up @@ -30,6 +30,12 @@ include "RISCVCallingConv.td"
include "RISCVInstrInfo.td"
include "GISel/RISCVRegisterBanks.td"

//===----------------------------------------------------------------------===//
// RISC-V macro fusions.
//===----------------------------------------------------------------------===//

include "RISCVMacroFusion.td"

//===----------------------------------------------------------------------===//
// RISC-V Scheduling Models
//===----------------------------------------------------------------------===//
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24 changes: 0 additions & 24 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1044,30 +1044,6 @@ def TuneDLenFactor2
: SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
"Vector unit DLEN(data path width) is half of VLEN">;

def TuneLUIADDIFusion
: SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
"true", "Enable LUI+ADDI macrofusion">;

def TuneAUIPCADDIFusion
: SubtargetFeature<"auipc-addi-fusion", "HasAUIPCADDIFusion",
"true", "Enable AUIPC+ADDI macrofusion">;

def TuneZExtHFusion
: SubtargetFeature<"zexth-fusion", "HasZExtHFusion",
"true", "Enable SLLI+SRLI to be fused to zero extension of halfword">;

def TuneZExtWFusion
: SubtargetFeature<"zextw-fusion", "HasZExtWFusion",
"true", "Enable SLLI+SRLI to be fused to zero extension of word">;

def TuneShiftedZExtWFusion
: SubtargetFeature<"shifted-zextw-fusion", "HasShiftedZExtWFusion",
"true", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension of word">;

def TuneLDADDFusion
: SubtargetFeature<"ld-add-fusion", "HasLDADDFusion",
"true", "Enable LD+ADD macrofusion.">;

def TuneNoDefaultUnroll
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
"Disable default unroll preference.">;
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210 changes: 0 additions & 210 deletions llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
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28 changes: 0 additions & 28 deletions llvm/lib/Target/RISCV/RISCVMacroFusion.h
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93 changes: 93 additions & 0 deletions llvm/lib/Target/RISCV/RISCVMacroFusion.td
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Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
//==----- RISCVMacroFusion.td - Macro Fusion Definitions -----*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

// ===---------------------------------------------------------------------===//
// The following definitions describe the macro fusion predicators.

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If we had a file MacroFusionUtils which contained same helper functions like checkIsVRegOperaned, would the same code written in C++ be much longer?

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The MacroFusionUtils can be useful to simplify TableGen-generated code. It's a good idea, I will try to implement this later!

// Fuse LUI followed by ADDI or ADDIW:
// rd = imm[31:0] which decomposes to
// lui rd, imm[31:12]
// addi(w) rd, rd, imm[11:0]
def TuneLUIADDIFusion
: SimpleFusion<"lui-addi-fusion", "HasLUIADDIFusion",
"Enable LUI+ADDI macro fusion",
CheckOpcode<[LUI]>,
CheckOpcode<[ADDI, ADDIW]>>;

// Fuse AUIPC followed by ADDI:
// auipc rd, imm20
// addi rd, rd, imm12
def TuneAUIPCADDIFusion
: SimpleFusion<"auipc-addi-fusion", "HasAUIPCADDIFusion",
"Enable AUIPC+ADDI macrofusion",
CheckOpcode<[AUIPC]>,
CheckOpcode<[ADDI]>>;

// Fuse zero extension of halfword:
// slli rd, rs1, 48
// srli rd, rd, 48
def TuneZExtHFusion
: SimpleFusion<"zexth-fusion", "HasZExtHFusion",
"Enable SLLI+SRLI to be fused to zero extension of halfword",
CheckAll<[
CheckOpcode<[SLLI]>,
CheckIsImmOperand<2>,
CheckImmOperand<2, 48>
]>,
CheckAll<[
CheckOpcode<[SRLI]>,
CheckIsImmOperand<2>,
CheckImmOperand<2, 48>
]>>;

// Fuse zero extension of word:
// slli rd, rs1, 32
// srli rd, rd, 32
def TuneZExtWFusion
: SimpleFusion<"zextw-fusion", "HasZExtWFusion",
"Enable SLLI+SRLI to be fused to zero extension of word",
CheckAll<[
CheckOpcode<[SLLI]>,
CheckIsImmOperand<2>,
CheckImmOperand<2, 32>
]>,
CheckAll<[
CheckOpcode<[SRLI]>,
CheckIsImmOperand<2>,
CheckImmOperand<2, 32>
]>>;

// Fuse shifted zero extension of word:
// slli rd, rs1, 32
// srli rd, rd, x
// where 0 <= x < 32
def TuneShiftedZExtWFusion
: SimpleFusion<"shifted-zextw-fusion", "HasShiftedZExtWFusion",
"Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
CheckAll<[
CheckOpcode<[SLLI]>,
CheckIsImmOperand<2>,
CheckImmOperand<2, 32>
]>,
CheckAll<[
CheckOpcode<[SRLI]>,
CheckIsImmOperand<2>,
CheckImmOperandRange<2, 0, 31>
]>>;

// Fuse load with add:
// add rd, rs1, rs2
// ld rd, 0(rd)
def TuneLDADDFusion
: SimpleFusion<"ld-add-fusion", "HasLDADDFusion", "Enable LD+ADD macrofusion",
CheckOpcode<[ADD]>,
CheckAll<[
CheckOpcode<[LD]>,
CheckIsImmOperand<2>,
CheckImmOperand<2, 0>
]>>;
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