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[InstCombine] Set disjoint flag when turning Add into Or. #72702

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Merged
merged 4 commits into from
Nov 27, 2023
Merged

[InstCombine] Set disjoint flag when turning Add into Or. #72702

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1d53b85
[InstCombine] Set disjoint flag when turning Add into Or.
topperc Nov 17, 2023
aca9ef2
fixup! update clang tests
topperc Nov 20, 2023
6a98a7e
fixup! Use cast after rebase.
topperc Nov 27, 2023
bd14f7c
fixup! update tests after rebase
topperc Nov 27, 2023
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12 changes: 6 additions & 6 deletions clang/test/CodeGen/aarch64-ls64-inline-asm.c
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Expand Up @@ -54,23 +54,23 @@ void store(const struct foo *input, void *addr)
// CHECK-NEXT: [[S_SROA_10_0_INSERT_SHIFT:%.*]] = shl nuw i512 [[S_SROA_10_0_INSERT_EXT]], 448
// CHECK-NEXT: [[S_SROA_9_0_INSERT_EXT:%.*]] = zext i64 [[CONV17]] to i512
// CHECK-NEXT: [[S_SROA_9_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_9_0_INSERT_EXT]], 384
// CHECK-NEXT: [[S_SROA_9_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_10_0_INSERT_SHIFT]], [[S_SROA_9_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_9_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_10_0_INSERT_SHIFT]], [[S_SROA_9_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_8_0_INSERT_EXT:%.*]] = zext i64 [[CONV14]] to i512
// CHECK-NEXT: [[S_SROA_8_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_8_0_INSERT_EXT]], 320
// CHECK-NEXT: [[S_SROA_8_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_9_0_INSERT_INSERT]], [[S_SROA_8_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_8_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_9_0_INSERT_INSERT]], [[S_SROA_8_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_7_0_INSERT_EXT:%.*]] = zext i64 [[CONV11]] to i512
// CHECK-NEXT: [[S_SROA_7_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_7_0_INSERT_EXT]], 256
// CHECK-NEXT: [[S_SROA_7_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_8_0_INSERT_INSERT]], [[S_SROA_7_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_7_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_8_0_INSERT_INSERT]], [[S_SROA_7_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_6_0_INSERT_EXT:%.*]] = zext i64 [[CONV8]] to i512
// CHECK-NEXT: [[S_SROA_6_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_6_0_INSERT_EXT]], 192
// CHECK-NEXT: [[S_SROA_6_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_7_0_INSERT_INSERT]], [[S_SROA_6_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_6_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_7_0_INSERT_INSERT]], [[S_SROA_6_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_5_0_INSERT_EXT:%.*]] = zext i64 [[CONV5]] to i512
// CHECK-NEXT: [[S_SROA_5_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_5_0_INSERT_EXT]], 128
// CHECK-NEXT: [[S_SROA_4_0_INSERT_EXT:%.*]] = zext i64 [[CONV2]] to i512
// CHECK-NEXT: [[S_SROA_4_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_4_0_INSERT_EXT]], 64
// CHECK-NEXT: [[S_SROA_4_0_INSERT_MASK:%.*]] = or i512 [[S_SROA_6_0_INSERT_INSERT]], [[S_SROA_5_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_4_0_INSERT_MASK:%.*]] = or disjoint i512 [[S_SROA_6_0_INSERT_INSERT]], [[S_SROA_5_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_0_0_INSERT_EXT:%.*]] = zext i64 [[CONV]] to i512
// CHECK-NEXT: [[S_SROA_0_0_INSERT_MASK:%.*]] = or i512 [[S_SROA_4_0_INSERT_MASK]], [[S_SROA_4_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_0_0_INSERT_MASK:%.*]] = or disjoint i512 [[S_SROA_4_0_INSERT_MASK]], [[S_SROA_4_0_INSERT_SHIFT]]
// CHECK-NEXT: [[S_SROA_0_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_0_0_INSERT_MASK]], [[S_SROA_0_0_INSERT_EXT]]
// CHECK-NEXT: tail call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 [[S_SROA_0_0_INSERT_INSERT]], ptr [[ADDR:%.*]]) #[[ATTR1]], !srcloc !8
// CHECK-NEXT: ret void
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGen/ms-intrinsics.c
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Expand Up @@ -444,7 +444,7 @@ unsigned char test_InterlockedCompareExchange128(
// CHECK-64: [[EH:%[0-9]+]] = zext i64 %inc to i128
// CHECK-64: [[EL:%[0-9]+]] = zext i64 %inc1 to i128
// CHECK-64: [[EHS:%[0-9]+]] = shl nuw i128 [[EH]], 64
// CHECK-64: [[EXP:%[0-9]+]] = or i128 [[EHS]], [[EL]]
// CHECK-64: [[EXP:%[0-9]+]] = or disjoint i128 [[EHS]], [[EL]]
// CHECK-64: [[ORG:%[0-9]+]] = load i128, ptr %incdec.ptr2, align 16
// CHECK-64: [[RES:%[0-9]+]] = cmpxchg volatile ptr %incdec.ptr, i128 [[ORG]], i128 [[EXP]] seq_cst seq_cst, align 16
// CHECK-64: [[OLD:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 0
Expand Down
7 changes: 5 additions & 2 deletions llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
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Expand Up @@ -1571,8 +1571,11 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {

// A+B --> A|B iff A and B have no bits set in common.
WithCache<const Value *> LHSCache(LHS), RHSCache(RHS);
if (haveNoCommonBitsSet(LHSCache, RHSCache, SQ.getWithInstruction(&I)))
return BinaryOperator::CreateOr(LHS, RHS);
if (haveNoCommonBitsSet(LHSCache, RHSCache, SQ.getWithInstruction(&I))) {
auto *Or = BinaryOperator::CreateOr(LHS, RHS);
cast<PossiblyDisjointInst>(Or)->setIsDisjoint(true);
return Or;
}
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Think there are a few places where xor -> or where we could also add disjoint.

https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp#L4485
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L296


if (Instruction *Ext = narrowMathIfNoOverflow(I))
return Ext;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Analysis/ValueTracking/assume.ll
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Expand Up @@ -7,7 +7,7 @@ define i32 @assume_add(i32 %a, i32 %b) {
; CHECK-NEXT: [[LAST_TWO_DIGITS:%.*]] = and i32 [[T1]], 3
; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[LAST_TWO_DIGITS]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = or i32 [[T1]], 3
; CHECK-NEXT: [[T3:%.*]] = or disjoint i32 [[T1]], 3
; CHECK-NEXT: ret i32 [[T3]]
;
%t1 = add i32 %a, %b
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/Transforms/InstCombine/add.ll
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Expand Up @@ -199,7 +199,7 @@ define i32 @test8(i32 %A, i32 %B) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: [[A1:%.*]] = and i32 [[A:%.*]], 7
; CHECK-NEXT: [[B1:%.*]] = and i32 [[B:%.*]], 128
; CHECK-NEXT: [[C:%.*]] = or i32 [[A1]], [[B1]]
; CHECK-NEXT: [[C:%.*]] = or disjoint i32 [[A1]], [[B1]]
; CHECK-NEXT: ret i32 [[C]]
;
%A1 = and i32 %A, 7
Expand Down Expand Up @@ -2565,7 +2565,7 @@ define i16 @add_sub_zext_constant(i8 %x) {
define <vscale x 1 x i32> @add_to_or_scalable(<vscale x 1 x i32> %in) {
; CHECK-LABEL: @add_to_or_scalable(
; CHECK-NEXT: [[SHL:%.*]] = shl <vscale x 1 x i32> [[IN:%.*]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
; CHECK-NEXT: [[ADD:%.*]] = or <vscale x 1 x i32> [[SHL]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
; CHECK-NEXT: [[ADD:%.*]] = or disjoint <vscale x 1 x i32> [[SHL]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
; CHECK-NEXT: ret <vscale x 1 x i32> [[ADD]]
;
%shl = shl <vscale x 1 x i32> %in, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
Expand Down Expand Up @@ -2626,7 +2626,7 @@ define i5 @zext_sext_not(i4 %x) {
; CHECK-NEXT: [[ZX:%.*]] = zext i4 [[X:%.*]] to i5
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
; CHECK-NEXT: [[SNOTX:%.*]] = sext i4 [[NOTX]] to i5
; CHECK-NEXT: [[R:%.*]] = or i5 [[ZX]], [[SNOTX]]
; CHECK-NEXT: [[R:%.*]] = or disjoint i5 [[ZX]], [[SNOTX]]
; CHECK-NEXT: ret i5 [[R]]
;
%zx = zext i4 %x to i5
Expand All @@ -2643,7 +2643,7 @@ define i8 @zext_sext_not_commute(i4 %x) {
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
; CHECK-NEXT: [[SNOTX:%.*]] = sext i4 [[NOTX]] to i8
; CHECK-NEXT: call void @use(i8 [[SNOTX]])
; CHECK-NEXT: [[R:%.*]] = or i8 [[SNOTX]], [[ZX]]
; CHECK-NEXT: [[R:%.*]] = or disjoint i8 [[SNOTX]], [[ZX]]
; CHECK-NEXT: ret i8 [[R]]
;
%zx = zext i4 %x to i8
Expand All @@ -2660,7 +2660,7 @@ define i9 @sext_zext_not(i4 %x) {
; CHECK-NEXT: [[SX:%.*]] = sext i4 [[X:%.*]] to i9
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
; CHECK-NEXT: [[ZNOTX:%.*]] = zext i4 [[NOTX]] to i9
; CHECK-NEXT: [[R:%.*]] = or i9 [[SX]], [[ZNOTX]]
; CHECK-NEXT: [[R:%.*]] = or disjoint i9 [[SX]], [[ZNOTX]]
; CHECK-NEXT: ret i9 [[R]]
;
%sx = sext i4 %x to i9
Expand All @@ -2675,7 +2675,7 @@ define i9 @sext_zext_not_commute(i4 %x) {
; CHECK-NEXT: [[SX:%.*]] = sext i4 [[X:%.*]] to i9
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
; CHECK-NEXT: [[ZNOTX:%.*]] = zext i4 [[NOTX]] to i9
; CHECK-NEXT: [[R:%.*]] = or i9 [[ZNOTX]], [[SX]]
; CHECK-NEXT: [[R:%.*]] = or disjoint i9 [[ZNOTX]], [[SX]]
; CHECK-NEXT: ret i9 [[R]]
;
%sx = sext i4 %x to i9
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Transforms/InstCombine/add2.ll
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Expand Up @@ -28,7 +28,7 @@ define i32 @test3(i32 %A) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], 128
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[A]], 30
; CHECK-NEXT: [[F:%.*]] = or i32 [[B]], [[C]]
; CHECK-NEXT: [[F:%.*]] = or disjoint i32 [[B]], [[C]]
; CHECK-NEXT: ret i32 [[F]]
;
%B = and i32 %A, 128
Expand Down Expand Up @@ -330,7 +330,7 @@ define i16 @mul_add_to_mul_9(i16 %a) {
define i16 @add_cttz(i16 %a) {
; CHECK-LABEL: @add_cttz(
; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -8
; CHECK-NEXT: [[B:%.*]] = or disjoint i16 [[CTTZ]], -8
; CHECK-NEXT: ret i16 [[B]]
;
; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned
Expand All @@ -352,7 +352,7 @@ declare i16 @llvm.cttz.i16(i16, i1)
define i16 @add_cttz_2(i16 %a) {
; CHECK-LABEL: @add_cttz_2(
; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range [[RNG1:![0-9]+]]
; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -16
; CHECK-NEXT: [[B:%.*]] = or disjoint i16 [[CTTZ]], -16
; CHECK-NEXT: ret i16 [[B]]
;
; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/apint-add.ll
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Expand Up @@ -149,7 +149,7 @@ define i128 @test8(i128 %x) {
define i77 @test9(i77 %x) {
; CHECK-LABEL: @test9(
; CHECK-NEXT: [[TMP_2:%.*]] = and i77 [[X:%.*]], 562949953421310
; CHECK-NEXT: [[TMP_4:%.*]] = or i77 [[TMP_2]], 1
; CHECK-NEXT: [[TMP_4:%.*]] = or disjoint i77 [[TMP_2]], 1
; CHECK-NEXT: ret i77 [[TMP_4]]
;
%tmp.2 = and i77 %x, 562949953421310
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/apint-shift.ll
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Expand Up @@ -481,7 +481,7 @@ define i44 @shl_lshr_eq_amt_multi_use(i44 %A) {
; CHECK-LABEL: @shl_lshr_eq_amt_multi_use(
; CHECK-NEXT: [[B:%.*]] = shl i44 [[A:%.*]], 33
; CHECK-NEXT: [[C:%.*]] = and i44 [[A]], 2047
; CHECK-NEXT: [[D:%.*]] = or i44 [[B]], [[C]]
; CHECK-NEXT: [[D:%.*]] = or disjoint i44 [[B]], [[C]]
; CHECK-NEXT: ret i44 [[D]]
;
%B = shl i44 %A, 33
Expand All @@ -496,7 +496,7 @@ define <2 x i44> @shl_lshr_eq_amt_multi_use_splat_vec(<2 x i44> %A) {
; CHECK-LABEL: @shl_lshr_eq_amt_multi_use_splat_vec(
; CHECK-NEXT: [[B:%.*]] = shl <2 x i44> [[A:%.*]], <i44 33, i44 33>
; CHECK-NEXT: [[C:%.*]] = and <2 x i44> [[A]], <i44 2047, i44 2047>
; CHECK-NEXT: [[D:%.*]] = or <2 x i44> [[B]], [[C]]
; CHECK-NEXT: [[D:%.*]] = or disjoint <2 x i44> [[B]], [[C]]
; CHECK-NEXT: ret <2 x i44> [[D]]
;
%B = shl <2 x i44> %A, <i44 33, i44 33>
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll
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Expand Up @@ -48,7 +48,7 @@ define i8 @add_bitreverse(i8 %a) {
; CHECK-LABEL: @add_bitreverse(
; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -4
; CHECK-NEXT: [[REVERSE:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[B]]), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[C:%.*]] = or i8 [[REVERSE]], -16
; CHECK-NEXT: [[C:%.*]] = or disjoint i8 [[REVERSE]], -16
; CHECK-NEXT: ret i8 [[C]]
;
%b = and i8 %a, 252
Expand Down
34 changes: 17 additions & 17 deletions llvm/test/Transforms/InstCombine/masked-merge-add.ll
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Expand Up @@ -21,7 +21,7 @@ define i32 @p(i32 %x, i32 %y, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: ret i32 [[RET]]
;
%and = and i32 %x, %m
Expand All @@ -36,7 +36,7 @@ define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) {
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor <2 x i32> [[M]], <i32 -1, i32 -1>
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint <2 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: ret <2 x i32> [[RET]]
;
%and = and <2 x i32> %x, %m
Expand All @@ -51,7 +51,7 @@ define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> %m) {
; CHECK-NEXT: [[AND:%.*]] = and <3 x i32> [[X:%.*]], [[M:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor <3 x i32> [[M]], <i32 -1, i32 undef, i32 -1>
; CHECK-NEXT: [[AND1:%.*]] = and <3 x i32> [[NEG]], [[Y:%.*]]
; CHECK-NEXT: [[RET:%.*]] = or <3 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint <3 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: ret <3 x i32> [[RET]]
;
%and = and <3 x i32> %x, %m
Expand All @@ -69,7 +69,7 @@ define i32 @p_constmask(i32 %x, i32 %y) {
; CHECK-LABEL: @p_constmask(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 65280
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: ret i32 [[RET]]
;
%and = and i32 %x, 65280
Expand All @@ -82,7 +82,7 @@ define <2 x i32> @p_constmask_splatvec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @p_constmask_splatvec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 65280, i32 65280>
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[Y:%.*]], <i32 -65281, i32 -65281>
; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint <2 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: ret <2 x i32> [[RET]]
;
%and = and <2 x i32> %x, <i32 65280, i32 65280>
Expand Down Expand Up @@ -125,7 +125,7 @@ define i32 @p_constmask2(i32 %x, i32 %y) {
; CHECK-LABEL: @p_constmask2(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 61440
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: ret i32 [[RET]]
;
%and = and i32 %x, 61440
Expand All @@ -138,7 +138,7 @@ define <2 x i32> @p_constmask2_splatvec(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @p_constmask2_splatvec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 61440, i32 61440>
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[Y:%.*]], <i32 -65281, i32 -65281>
; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint <2 x i32> [[AND]], [[AND1]]
; CHECK-NEXT: ret <2 x i32> [[RET]]
;
%and = and <2 x i32> %x, <i32 61440, i32 61440>
Expand Down Expand Up @@ -185,7 +185,7 @@ define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: ret i32 [[RET]]
;
%and = and i32 %m, %x ; swapped order
Expand All @@ -201,7 +201,7 @@ define i32 @p_commutative1(i32 %x, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: ret i32 [[RET]]
;
%y = call i32 @gen32()
Expand All @@ -217,7 +217,7 @@ define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
; CHECK-NEXT: ret i32 [[RET]]
;
%and = and i32 %x, %m
Expand All @@ -233,7 +233,7 @@ define i32 @p_commutative3(i32 %x, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: ret i32 [[RET]]
;
%y = call i32 @gen32()
Expand All @@ -249,7 +249,7 @@ define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
; CHECK-NEXT: ret i32 [[RET]]
;
%and = and i32 %m, %x ; swapped order
Expand All @@ -265,7 +265,7 @@ define i32 @p_commutative5(i32 %x, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
; CHECK-NEXT: ret i32 [[RET]]
;
%y = call i32 @gen32()
Expand All @@ -282,7 +282,7 @@ define i32 @p_commutative6(i32 %x, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
; CHECK-NEXT: ret i32 [[RET]]
;
%y = call i32 @gen32()
Expand All @@ -297,7 +297,7 @@ define i32 @p_constmask_commutative(i32 %x, i32 %y) {
; CHECK-LABEL: @p_constmask_commutative(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 65280
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
; CHECK-NEXT: ret i32 [[RET]]
;
%and = and i32 %x, 65280
Expand All @@ -319,7 +319,7 @@ define i32 @n0_oneuse(i32 %x, i32 %y, i32 %m) {
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: call void @use32(i32 [[AND]])
; CHECK-NEXT: call void @use32(i32 [[NEG]])
; CHECK-NEXT: call void @use32(i32 [[AND1]])
Expand All @@ -339,7 +339,7 @@ define i32 @n0_constmask_oneuse(i32 %x, i32 %y) {
; CHECK-LABEL: @n0_constmask_oneuse(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 65280
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
; CHECK-NEXT: call void @use32(i32 [[AND]])
; CHECK-NEXT: call void @use32(i32 [[AND1]])
; CHECK-NEXT: ret i32 [[RET]]
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
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Expand Up @@ -1934,7 +1934,7 @@ define i8 @smax_offset_uses(i8 %x) {
define <3 x i8> @smin_offset(<3 x i8> %x) {
; CHECK-LABEL: @smin_offset(
; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i8> @llvm.smin.v3i8(<3 x i8> [[X:%.*]], <3 x i8> <i8 -127, i8 -127, i8 -127>)
; CHECK-NEXT: [[M:%.*]] = or <3 x i8> [[TMP1]], <i8 124, i8 124, i8 124>
; CHECK-NEXT: [[M:%.*]] = or disjoint <3 x i8> [[TMP1]], <i8 124, i8 124, i8 124>
; CHECK-NEXT: ret <3 x i8> [[M]]
;
%a = add nsw nuw <3 x i8> %x, <i8 124, i8 124, i8 124>
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/or.ll
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Expand Up @@ -1476,7 +1476,7 @@ define i32 @mul_no_common_bits(i32 %p1, i32 %p2) {
; CHECK-LABEL: @mul_no_common_bits(
; CHECK-NEXT: [[X:%.*]] = and i32 [[P1:%.*]], 7
; CHECK-NEXT: [[Y:%.*]] = shl i32 [[P2:%.*]], 3
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[Y]], 1
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i32 [[Y]], 1
; CHECK-NEXT: [[R:%.*]] = mul i32 [[X]], [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/pr72433.ll
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Expand Up @@ -9,7 +9,7 @@ define i32 @widget(i32 %arg, i32 %arg1) {
; CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[ICMP]] to i32
; CHECK-NEXT: [[MUL:%.*]] = shl nuw nsw i32 20, [[TMP0]]
; CHECK-NEXT: [[XOR:%.*]] = zext i1 [[ICMP]] to i32
; CHECK-NEXT: [[ADD9:%.*]] = or i32 [[MUL]], [[XOR]]
; CHECK-NEXT: [[ADD9:%.*]] = or disjoint i32 [[MUL]], [[XOR]]
; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[ICMP]] to i32
; CHECK-NEXT: [[MUL2:%.*]] = shl nuw nsw i32 [[ADD9]], [[TMP1]]
; CHECK-NEXT: ret i32 [[MUL2]]
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/ptrtoint-nullgep.ll
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Expand Up @@ -602,7 +602,7 @@ define i64 @fold_ptrtoint_nested_array_two_vars_plus_const(i64 %x, i64 %y) {
; INSTCOMBINE-NEXT: [[PTR_IDX:%.*]] = shl i64 [[X]], 3
; INSTCOMBINE-NEXT: [[PTR_IDX1:%.*]] = shl i64 [[Y]], 2
; INSTCOMBINE-NEXT: [[PTR_OFFS:%.*]] = add i64 [[PTR_IDX]], [[PTR_IDX1]]
; INSTCOMBINE-NEXT: [[PTR_OFFS2:%.*]] = or i64 [[PTR_OFFS]], 2
; INSTCOMBINE-NEXT: [[PTR_OFFS2:%.*]] = or disjoint i64 [[PTR_OFFS]], 2
; INSTCOMBINE-NEXT: ret i64 [[PTR_OFFS2]]
;
%ptr = getelementptr [2 x [2 x i16]], ptr addrspace(1) null, i64 %x, i64 %y, i64 1
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