[RISCV] Rework IDiv and FDiv pipes on SiFive7

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

@@ -213,12 +213,12 @@ let SchedModel = SiFive7Model in {
 let BufferSize = 0 in {
 def SiFive7PipeA       : ProcResource<1>;
 def SiFive7PipeB       : ProcResource<1>;
+def SiFive7IDiv        : ProcResource<1>; // Int Division
+def SiFive7FDiv        : ProcResource<1>; // FP Division/Sqrt
 def SiFive7PipeV       : ProcResource<1>;
 }
 
 let BufferSize = 1 in {
-def SiFive7IDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
-def SiFive7FDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
 def SiFive7VA          : ProcResource<1> { let Super = SiFive7PipeV; } // Arithmetic sequencer
 def SiFive7VL          : ProcResource<1> { let Super = SiFive7PipeV; } // Load sequencer
 def SiFive7VS          : ProcResource<1> { let Super = SiFive7PipeV; } // Store sequencer

llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s

@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-u74 -timeline -iterations=1 < %s \
+# RUN:   | FileCheck %s
+
+div a0, a1, a2
+fdiv.s f1, f2, f3
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK-NEXT: Total Cycles:      67
+# CHECK-NEXT: Total uOps:        2
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.03
+# CHECK-NEXT: IPC:               0.03
+# CHECK-NEXT: Block RThroughput: 65.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      66    65.00                       div	a0, a1, a2
+# CHECK-NEXT:  1      27    26.00                       fdiv.s	ft1, ft2, ft3
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT: 26.00  65.00   -     2.00    -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -     65.00   -     1.00    -      -      -      -     div	a0, a1, a2
+# CHECK-NEXT: 26.00   -      -     1.00    -      -      -      -     fdiv.s	ft1, ft2, ft3
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                     0123456789          0123456789          0123456789
+# CHECK-NEXT: Index     0123456789          0123456789          0123456789          0123456
+
+# CHECK:      [0,0]     DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE   div	a0, a1, a2
+# CHECK-NEXT: [0,1]     .    .    .    .    .    .    .    .   DeeeeeeeeeeeeeeeeeeeeeeeeeeE   fdiv.s	ft1, ft2, ft3
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       div	a0, a1, a2
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       fdiv.s	ft1, ft2, ft3
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>