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[AArch64] Assembly support for the Armv9.5-A RAS Extensions #76161

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Dec 22, 2023
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[AArch64] Assembly support for the Armv9.5-A RAS Extensions #76161

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5 changes: 5 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SystemOperands.td
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Expand Up @@ -1946,3 +1946,8 @@ def : RWSysReg<"MDSTEPOP_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b010>;
// v9.5a System PMU zero register (FEAT_SPMU2)
// Op0 Op1 CRn CRm Op2
def : WOSysReg<"SPMZR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b100>;

// v9.5a Delegated SError exceptions for EL3 (FEAT_E3DSE)
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"VDISR_EL3", 0b11, 0b110, 0b1100, 0b0001, 0b001>;
def : RWSysReg<"VSESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b011>;
13 changes: 13 additions & 0 deletions llvm/test/MC/AArch64/armv9.5a-e3dse.s
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@@ -0,0 +1,13 @@
// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s

mrs x0, VDISR_EL3
// CHECK: mrs x0, VDISR_EL3 // encoding: [0x20,0xc1,0x3e,0xd5]

msr VDISR_EL3, x0
// CHECK: msr VDISR_EL3, x0 // encoding: [0x20,0xc1,0x1e,0xd5]

mrs x0, VSESR_EL3
// CHECK: mrs x0, VSESR_EL3 // encoding: [0x60,0x52,0x3e,0xd5]

msr VSESR_EL3, x0
// CHECK: msr VSESR_EL3, x0 // encoding: [0x60,0x52,0x1e,0xd5]
13 changes: 13 additions & 0 deletions llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt
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# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s

[0x20,0xc1,0x3e,0xd5]
# CHECK: mrs x0, VDISR_EL3

[0x20,0xc1,0x1e,0xd5]
# CHECK: msr VDISR_EL3, x0

[0x60,0x52,0x3e,0xd5]
# CHECK: mrs x0, VSESR_EL3

[0x60,0x52,0x1e,0xd5]
# CHECK: msr VSESR_EL3, x0