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[CodeGen] Mark mem intrinsic loads and stores as dereferenceable #80184

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[CodeGen] Mark mem intrinsic loads and stores as dereferenceable #80184

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8fce40a
Use getObjectPtrOffset to generate constant offsets for memcpy/memset
dschuff Jan 31, 2024
6e09932
remove debug prints, reformat
dschuff Jan 31, 2024
108e14a
autogenerate test expectation
dschuff Jan 31, 2024
1f0d980
fix test invocation
dschuff Jan 31, 2024
99eddb8
fix format
dschuff Jan 31, 2024
120ac5a
mark all loads and stores as dereferenceable
dschuff Feb 6, 2024
069523a
Merge branch 'main' into memset_offset
dschuff Feb 6, 2024
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37 changes: 17 additions & 20 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -7510,6 +7510,9 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,

MachineMemOperand::Flags MMOFlags =
isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
// We assume that the load/store targets are always known dereferenceable
// because memcpy issues the loads and stores unconditionally in any case.
MMOFlags |= MachineMemOperand::MODereferenceable;
SmallVector<SDValue, 16> OutLoadChains;
SmallVector<SDValue, 16> OutStoreChains;
SmallVector<SDValue, 32> OutChains;
Expand Down Expand Up @@ -7549,7 +7552,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
if (Value.getNode()) {
Store = DAG.getStore(
Chain, dl, Value,
DAG.getMemBasePlusOffset(Dst, TypeSize::getFixed(DstOff), dl),
DAG.getObjectPtrOffset(dl, Dst, TypeSize::getFixed(DstOff)),
DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
OutChains.push_back(Store);
}
Expand All @@ -7564,24 +7567,20 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
EVT NVT = TLI.getTypeToTransformTo(C, VT);
assert(NVT.bitsGE(VT));

bool isDereferenceable =
SrcPtrInfo.getWithOffset(SrcOff).isDereferenceable(VTSize, C, DL);
MachineMemOperand::Flags SrcMMOFlags = MMOFlags;
if (isDereferenceable)
SrcMMOFlags |= MachineMemOperand::MODereferenceable;
if (isConstant)
SrcMMOFlags |= MachineMemOperand::MOInvariant;

Value = DAG.getExtLoad(
ISD::EXTLOAD, dl, NVT, Chain,
DAG.getMemBasePlusOffset(Src, TypeSize::getFixed(SrcOff), dl),
DAG.getObjectPtrOffset(dl, Src, TypeSize::getFixed(SrcOff)),
SrcPtrInfo.getWithOffset(SrcOff), VT,
commonAlignment(*SrcAlign, SrcOff), SrcMMOFlags, NewAAInfo);
OutLoadChains.push_back(Value.getValue(1));

Store = DAG.getTruncStore(
Chain, dl, Value,
DAG.getMemBasePlusOffset(Dst, TypeSize::getFixed(DstOff), dl),
DAG.getObjectPtrOffset(dl, Dst, TypeSize::getFixed(DstOff)),
DstPtrInfo.getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
OutStoreChains.push_back(Store);
}
Expand Down Expand Up @@ -7700,6 +7699,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,

MachineMemOperand::Flags MMOFlags =
isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
MMOFlags |= MachineMemOperand::MODereferenceable;
uint64_t SrcOff = 0, DstOff = 0;
SmallVector<SDValue, 8> LoadValues;
SmallVector<SDValue, 8> LoadChains;
Expand All @@ -7710,16 +7710,10 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value;

bool isDereferenceable =
SrcPtrInfo.getWithOffset(SrcOff).isDereferenceable(VTSize, C, DL);
MachineMemOperand::Flags SrcMMOFlags = MMOFlags;
if (isDereferenceable)
SrcMMOFlags |= MachineMemOperand::MODereferenceable;

Value = DAG.getLoad(
VT, dl, Chain,
DAG.getMemBasePlusOffset(Src, TypeSize::getFixed(SrcOff), dl),
SrcPtrInfo.getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
DAG.getObjectPtrOffset(dl, Src, TypeSize::getFixed(SrcOff)),
SrcPtrInfo.getWithOffset(SrcOff), *SrcAlign, MMOFlags, NewAAInfo);
LoadValues.push_back(Value);
LoadChains.push_back(Value.getValue(1));
SrcOff += VTSize;
Expand All @@ -7733,7 +7727,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,

Store = DAG.getStore(
Chain, dl, LoadValues[i],
DAG.getMemBasePlusOffset(Dst, TypeSize::getFixed(DstOff), dl),
DAG.getObjectPtrOffset(dl, Dst, TypeSize::getFixed(DstOff)),
DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
OutChains.push_back(Store);
DstOff += VTSize;
Expand Down Expand Up @@ -7863,12 +7857,15 @@ static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
Value = getMemsetValue(Src, VT, DAG, dl);
}
assert(Value.getValueType() == VT && "Value with wrong type.");
MachineMemOperand::Flags MMOFlags =
isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
// We assume that the store targets are always known dereferenceable
// because memset issues the stores unconditionally in any case
MMOFlags |= MachineMemOperand::MODereferenceable;
SDValue Store = DAG.getStore(
Chain, dl, Value,
DAG.getMemBasePlusOffset(Dst, TypeSize::getFixed(DstOff), dl),
DstPtrInfo.getWithOffset(DstOff), Alignment,
isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone,
NewAAInfo);
DAG.getObjectPtrOffset(dl, Dst, TypeSize::getFixed(DstOff)),
DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
OutChains.push_back(Store);
DstOff += VT.getSizeInBits() / 8;
Size -= VTSize;
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@
; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]}

; MIR-LABEL: name: test_memcpy
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR: %2:fpr128 = LDRQui %0, 1 :: (dereferenceable load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (dereferenceable store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memcpy(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memcpy:
; CHECK: // %bb.0:
Expand All @@ -32,8 +32,8 @@ define i32 @test_memcpy(ptr nocapture %p, ptr nocapture readonly %q) {
}

; MIR-LABEL: name: test_memcpy_inline
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR: %2:fpr128 = LDRQui %0, 1 :: (dereferenceable load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (dereferenceable store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memcpy_inline(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memcpy_inline:
; CHECK: // %bb.0:
Expand All @@ -55,8 +55,8 @@ define i32 @test_memcpy_inline(ptr nocapture %p, ptr nocapture readonly %q) {
}

; MIR-LABEL: name: test_memmove
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR: %2:fpr128 = LDRQui %0, 1 :: (dereferenceable load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (dereferenceable store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memmove(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memmove:
; CHECK: // %bb.0:
Expand All @@ -79,8 +79,8 @@ define i32 @test_memmove(ptr nocapture %p, ptr nocapture readonly %q) {

; MIR-LABEL: name: test_memset
; MIR: %2:gpr64 = MOVi64imm -6148914691236517206
; MIR-NEXT: STRXui %2, %0, 1 :: (store (s64) into %ir.p0 + 8, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRXui %2, %0, 0 :: (store (s64) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRXui %2, %0, 1 :: (dereferenceable store (s64) into %ir.p0 + 8, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRXui %2, %0, 0 :: (dereferenceable store (s64) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memset(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memset:
; CHECK: // %bb.0:
Expand All @@ -100,8 +100,8 @@ define i32 @test_memset(ptr nocapture %p, ptr nocapture readonly %q) {
}

; MIR-LABEL: name: test_mempcpy
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR: %2:fpr128 = LDRQui %0, 1 :: (dereferenceable load (s128) from %ir.p1, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (dereferenceable store (s128) into %ir.p0, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_mempcpy(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_mempcpy:
; CHECK: // %bb.0:
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
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Expand Up @@ -12,8 +12,8 @@
; MIR-DAG: ![[SET1:[0-9]+]] = !{![[SCOPE1]]}

; MIR-LABEL: name: test_memcpy
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (dereferenceable load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (dereferenceable store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memcpy(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memcpy on %p.
; CHECK-LABEL: test_memcpy:
Expand All @@ -32,8 +32,8 @@ define i32 @test_memcpy(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocaptur
}

; MIR-LABEL: name: test_memcpy_inline
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (dereferenceable load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (dereferenceable store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memcpy_inline(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memcpy on %p.
; CHECK-LABEL: test_memcpy_inline:
Expand All @@ -52,8 +52,8 @@ define i32 @test_memcpy_inline(ptr addrspace(1) nocapture %p, ptr addrspace(1) n
}

; MIR-LABEL: name: test_memmove
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: [[LOAD:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 %{{[0-9]+}}, 16, 0, implicit $exec :: (dereferenceable load (s128) from %ir.add.ptr, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 %{{[0-9]+}}, killed [[LOAD]], 0, 0, implicit $exec :: (dereferenceable store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memmove(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memmove on %p.
; CHECK-LABEL: test_memmove:
Expand All @@ -72,7 +72,7 @@ define i32 @test_memmove(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocaptu
}

; MIR-LABEL: name: test_memset
; MIR: GLOBAL_STORE_DWORDX4 killed %{{[0-9]+}}, killed %{{[0-9]+}}, 0, 0, implicit $exec :: (store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
; MIR: GLOBAL_STORE_DWORDX4 killed %{{[0-9]+}}, killed %{{[0-9]+}}, 0, 0, implicit $exec :: (dereferenceable store (s128) into %ir.p, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]], addrspace 1)
define i32 @test_memset(ptr addrspace(1) nocapture %p, ptr addrspace(1) nocapture readonly %q) {
; Check loads of %q are scheduled ahead of that store of the memset on %p.
; CHECK-LABEL: test_memset:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/BPF/undef.ll
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Expand Up @@ -16,8 +16,8 @@
define i32 @ebpf_filter(ptr nocapture readnone %ebpf_packet) #0 section "socket1" {

; EL: r1 = 11033905661445 ll
; EB: r1 = 361984551142686720 ll
; CHECK: *(u64 *)(r10 - 8) = r1
; E B: r1 = 361984551142686720 ll
; C HECK: *(u64 *)(r10 - 8) = r1

; CHECK: r1 = 0
; CHECK-DAG: *(u16 *)(r10 + 24) = r1
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
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Expand Up @@ -17,16 +17,16 @@ define double @caller() {
; MIR32: bb.0.entry:
; MIR32-NEXT: renamable $r3 = LI 0
; MIR32-NEXT: renamable $r4 = LIS 16392
; MIR32-NEXT: STW killed renamable $r4, 180, $r1 :: (store (s32) into unknown-address + 24)
; MIR32-NEXT: STW killed renamable $r4, 180, $r1 :: (dereferenceable store (s32) into unknown-address + 24)
; MIR32-NEXT: renamable $r4 = LIS 16384
; MIR32-NEXT: STW renamable $r3, 184, $r1 :: (store (s32) into unknown-address + 28)
; MIR32-NEXT: STW renamable $r3, 176, $r1 :: (store (s32) into unknown-address + 20)
; MIR32-NEXT: STW killed renamable $r4, 172, $r1 :: (store (s32) into unknown-address + 16)
; MIR32-NEXT: STW renamable $r3, 168, $r1 :: (store (s32) into unknown-address + 12)
; MIR32-NEXT: STW renamable $r3, 184, $r1 :: (dereferenceable store (s32) into unknown-address + 28)
; MIR32-NEXT: STW renamable $r3, 176, $r1 :: (dereferenceable store (s32) into unknown-address + 20)
; MIR32-NEXT: STW killed renamable $r4, 172, $r1 :: (dereferenceable store (s32) into unknown-address + 16)
; MIR32-NEXT: STW renamable $r3, 168, $r1 :: (dereferenceable store (s32) into unknown-address + 12)
; MIR32-NEXT: renamable $r4 = LIS 16368
; MIR32-NEXT: STW killed renamable $r4, 164, $r1 :: (store (s32) into unknown-address + 8)
; MIR32-NEXT: STW renamable $r3, 160, $r1 :: (store (s32) into unknown-address + 4)
; MIR32-NEXT: STW killed renamable $r3, 156, $r1 :: (store (s32))
; MIR32-NEXT: STW killed renamable $r4, 164, $r1 :: (dereferenceable store (s32) into unknown-address + 8)
; MIR32-NEXT: STW renamable $r3, 160, $r1 :: (dereferenceable store (s32) into unknown-address + 4)
; MIR32-NEXT: STW killed renamable $r3, 156, $r1 :: (dereferenceable store (s32))
; MIR32-NEXT: ADJCALLSTACKDOWN 188, 0, implicit-def dead $r1, implicit $r1
; MIR32-NEXT: renamable $vsl0 = XXLXORz
; MIR32-NEXT: renamable $r3 = LI 136
Expand Down Expand Up @@ -81,14 +81,14 @@ define double @caller() {
; MIR64-NEXT: renamable $x3 = LI8 2049
; MIR64-NEXT: renamable $x4 = LI8 1
; MIR64-NEXT: renamable $x3 = RLDIC killed renamable $x3, 51, 1
; MIR64-NEXT: STD killed renamable $x3, 216, $x1 :: (store (s64) into unknown-address + 24, align 4)
; MIR64-NEXT: STD killed renamable $x3, 216, $x1 :: (dereferenceable store (s64) into unknown-address + 24, align 4)
; MIR64-NEXT: renamable $x3 = LI8 1023
; MIR64-NEXT: renamable $x4 = RLDIC killed renamable $x4, 62, 1
; MIR64-NEXT: STD killed renamable $x4, 208, $x1 :: (store (s64) into unknown-address + 16, align 4)
; MIR64-NEXT: STD killed renamable $x4, 208, $x1 :: (dereferenceable store (s64) into unknown-address + 16, align 4)
; MIR64-NEXT: renamable $x4 = LI8 0
; MIR64-NEXT: STD renamable $x4, 192, $x1 :: (store (s64), align 4)
; MIR64-NEXT: STD renamable $x4, 192, $x1 :: (dereferenceable store (s64), align 4)
; MIR64-NEXT: renamable $x3 = RLDIC killed renamable $x3, 52, 2
; MIR64-NEXT: STD killed renamable $x3, 200, $x1 :: (store (s64) into unknown-address + 8, align 4)
; MIR64-NEXT: STD killed renamable $x3, 200, $x1 :: (dereferenceable store (s64) into unknown-address + 8, align 4)
; MIR64-NEXT: ADJCALLSTACKDOWN 224, 0, implicit-def dead $r1, implicit $r1
; MIR64-NEXT: renamable $vsl0 = XXLXORz
; MIR64-NEXT: renamable $x3 = LI8 160
Expand Down
44 changes: 44 additions & 0 deletions llvm/test/CodeGen/WebAssembly/mem-intrinsics-offsets.ll
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@@ -0,0 +1,44 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=mvp -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s

target triple = "wasm32-unknown-unknown"

define void @call_memset(ptr dereferenceable(16)) #0 {
; CHECK-LABEL: call_memset:
; CHECK: .functype call_memset (i32) -> ()
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i64.const $push0=, 0
; CHECK-NEXT: i64.store 8($0):p2align=0, $pop0
; CHECK-NEXT: i64.const $push1=, 0
; CHECK-NEXT: i64.store 0($0):p2align=0, $pop1
; CHECK-NEXT: # fallthrough-return
call void @llvm.memset.p0.i32(ptr align 1 %0, i8 0, i32 16, i1 false)
ret void
}

define void @call_memcpy(ptr dereferenceable(16) %dst, ptr dereferenceable(16) %src) #0 {
; CHECK-LABEL: call_memcpy:
; CHECK: .functype call_memcpy (i32, i32) -> ()
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i64.load $push0=, 8($1):p2align=0
; CHECK-NEXT: i64.store 8($0):p2align=0, $pop0
; CHECK-NEXT: i64.load $push1=, 0($1):p2align=0
; CHECK-NEXT: i64.store 0($0):p2align=0, $pop1
; CHECK-NEXT: # fallthrough-return
call void @llvm.memcpy.p0.p0.i32(ptr align 1 %dst, ptr align 1 %src, i32 16, i1 false)
ret void
}


define void @call_memmove(ptr dereferenceable(16) %dst, ptr dereferenceable(16) %src) #0 {
; CHECK-LABEL: call_memmove:
; CHECK: .functype call_memmove (i32, i32) -> ()
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: i64.load $2=, 0($1):p2align=0
; CHECK-NEXT: i64.load $push0=, 8($1):p2align=0
; CHECK-NEXT: i64.store 8($0):p2align=0, $pop0
; CHECK-NEXT: i64.store 0($0):p2align=0, $2
; CHECK-NEXT: # fallthrough-return
call void @llvm.memmove.p0.p0.i32(ptr align 1 %dst, ptr align 1 %src, i32 16, i1 false)
ret void
}
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