[ARM][AArch64] Split FEAT_SHA1 from FEAT_SHA256. #99816
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These features can be detected individually in Function Multiversioning therefore we would like to support them as separate features.
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@llvm/pr-subscribers-backend-aarch64 @llvm/pr-subscribers-clang-driver Author: Alexandros Lamprineas (labrinea) ChangesThese features can be detected individually in Function Multiversioning therefore we would like to support them as separate features. Patch is 109.44 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/99816.diff 75 Files Affected:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 6349fcf3dadd7..6c98c23157e8f 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -728,6 +728,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
.Case("rdm", HasRDM)
.Case("lse", HasLSE)
.Case("crc", HasCRC)
+ .Case("sha1", HasSHA1)
.Case("sha2", HasSHA2)
.Case("sha3", HasSHA3)
.Cases("aes", "pmull", HasAES)
@@ -932,12 +933,18 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
FPU |= NeonMode;
HasAES = true;
}
+ if (Feature == "+sha1") {
+ FPU |= NeonMode;
+ HasSHA1 = true;
+ }
if (Feature == "+sha2") {
FPU |= NeonMode;
+ HasSHA1 = true;
HasSHA2 = true;
}
if (Feature == "+sha3") {
FPU |= NeonMode;
+ HasSHA1 = true;
HasSHA2 = true;
HasSHA3 = true;
}
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 7bdf5a2b4106e..1805199adf639 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -35,6 +35,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
unsigned FPU = FPUMode;
bool HasCRC = false;
bool HasAES = false;
+ bool HasSHA1 = false;
bool HasSHA2 = false;
bool HasSHA3 = false;
bool HasSM4 = false;
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 7423626d7c3cb..ed2cc8d1225b7 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -506,6 +506,7 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
CRC = 0;
Crypto = 0;
SHA2 = 0;
+ SHA1 = 0;
AES = 0;
DSP = 0;
HasUnalignedAccess = true;
@@ -563,6 +564,9 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
Crypto = 1;
} else if (Feature == "+sha2") {
SHA2 = 1;
+ SHA1 = 1;
+ } else if (Feature == "+sha1") {
+ SHA1 = 1;
} else if (Feature == "+aes") {
AES = 1;
} else if (Feature == "+dsp") {
diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h
index df9855a52e61c..df93c43c5729c 100644
--- a/clang/lib/Basic/Targets/ARM.h
+++ b/clang/lib/Basic/Targets/ARM.h
@@ -84,6 +84,8 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
LLVM_PREFERRED_TYPE(bool)
unsigned SHA2 : 1;
LLVM_PREFERRED_TYPE(bool)
+ unsigned SHA1 : 1;
+ LLVM_PREFERRED_TYPE(bool)
unsigned AES : 1;
LLVM_PREFERRED_TYPE(bool)
unsigned DSP : 1;
diff --git a/clang/test/CodeGen/aarch64-targetattr-crypto.c b/clang/test/CodeGen/aarch64-targetattr-crypto.c
index 006a394be7775..94e0c12a4a055 100644
--- a/clang/test/CodeGen/aarch64-targetattr-crypto.c
+++ b/clang/test/CodeGen/aarch64-targetattr-crypto.c
@@ -49,5 +49,5 @@ void test_sha2aes(uint8x16_t data, uint8x16_t key)
void test_errors(uint8x16_t data, uint8x16_t key)
{
vaeseq_u8(data, key); // expected-error {{always_inline function 'vaeseq_u8' requires target feature 'aes'}}
- vsha1su1q_u32(data, key); // expected-error {{always_inline function 'vsha1su1q_u32' requires target feature 'sha2'}}
+ vsha1su1q_u32(data, key); // expected-error {{always_inline function 'vsha1su1q_u32' requires target feature 'sha1'}}
}
diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b618..2d1308c6a0f7a 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -200,14 +200,14 @@ void minusarch() {}
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
-// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha1,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
-// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
+// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha1,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
+// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha1,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" }
-// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha1,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha1,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
//.
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c b/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
index 269aec5ad0845..ad79eb4fcc02a 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
@@ -18,7 +18,8 @@
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
index bc5edbc77c9b9..35bf75ffff9d8 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
@@ -44,7 +44,8 @@
// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
index 3c20cff28821e..182f6e4d055b0 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
@@ -45,7 +45,8 @@
// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
index 444ac4526200f..b7c244cbb75fb 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
@@ -47,7 +47,8 @@
// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
index aa8cc7bd3badd..30484dbe9cf45 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
@@ -12,5 +12,6 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
index d219981e6be3c..de3d0c2dd55d1 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
@@ -17,6 +17,7 @@
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
index 27f066a310708..ec0c148ca649c 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
@@ -22,6 +22,7 @@
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
index 197b210259951..6aff96c291a67 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
@@ -32,7 +32,8 @@
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
index f1731ef034a0c..e5dd2f1dc1451 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
@@ -37,7 +37,8 @@
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CH...
[truncated]
|
|
@llvm/pr-subscribers-backend-arm Author: Alexandros Lamprineas (labrinea) ChangesThese features can be detected individually in Function Multiversioning therefore we would like to support them as separate features. Patch is 109.44 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/99816.diff 75 Files Affected:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 6349fcf3dadd7..6c98c23157e8f 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -728,6 +728,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
.Case("rdm", HasRDM)
.Case("lse", HasLSE)
.Case("crc", HasCRC)
+ .Case("sha1", HasSHA1)
.Case("sha2", HasSHA2)
.Case("sha3", HasSHA3)
.Cases("aes", "pmull", HasAES)
@@ -932,12 +933,18 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
FPU |= NeonMode;
HasAES = true;
}
+ if (Feature == "+sha1") {
+ FPU |= NeonMode;
+ HasSHA1 = true;
+ }
if (Feature == "+sha2") {
FPU |= NeonMode;
+ HasSHA1 = true;
HasSHA2 = true;
}
if (Feature == "+sha3") {
FPU |= NeonMode;
+ HasSHA1 = true;
HasSHA2 = true;
HasSHA3 = true;
}
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 7bdf5a2b4106e..1805199adf639 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -35,6 +35,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
unsigned FPU = FPUMode;
bool HasCRC = false;
bool HasAES = false;
+ bool HasSHA1 = false;
bool HasSHA2 = false;
bool HasSHA3 = false;
bool HasSM4 = false;
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 7423626d7c3cb..ed2cc8d1225b7 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -506,6 +506,7 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
CRC = 0;
Crypto = 0;
SHA2 = 0;
+ SHA1 = 0;
AES = 0;
DSP = 0;
HasUnalignedAccess = true;
@@ -563,6 +564,9 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
Crypto = 1;
} else if (Feature == "+sha2") {
SHA2 = 1;
+ SHA1 = 1;
+ } else if (Feature == "+sha1") {
+ SHA1 = 1;
} else if (Feature == "+aes") {
AES = 1;
} else if (Feature == "+dsp") {
diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h
index df9855a52e61c..df93c43c5729c 100644
--- a/clang/lib/Basic/Targets/ARM.h
+++ b/clang/lib/Basic/Targets/ARM.h
@@ -84,6 +84,8 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
LLVM_PREFERRED_TYPE(bool)
unsigned SHA2 : 1;
LLVM_PREFERRED_TYPE(bool)
+ unsigned SHA1 : 1;
+ LLVM_PREFERRED_TYPE(bool)
unsigned AES : 1;
LLVM_PREFERRED_TYPE(bool)
unsigned DSP : 1;
diff --git a/clang/test/CodeGen/aarch64-targetattr-crypto.c b/clang/test/CodeGen/aarch64-targetattr-crypto.c
index 006a394be7775..94e0c12a4a055 100644
--- a/clang/test/CodeGen/aarch64-targetattr-crypto.c
+++ b/clang/test/CodeGen/aarch64-targetattr-crypto.c
@@ -49,5 +49,5 @@ void test_sha2aes(uint8x16_t data, uint8x16_t key)
void test_errors(uint8x16_t data, uint8x16_t key)
{
vaeseq_u8(data, key); // expected-error {{always_inline function 'vaeseq_u8' requires target feature 'aes'}}
- vsha1su1q_u32(data, key); // expected-error {{always_inline function 'vsha1su1q_u32' requires target feature 'sha2'}}
+ vsha1su1q_u32(data, key); // expected-error {{always_inline function 'vsha1su1q_u32' requires target feature 'sha1'}}
}
diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b618..2d1308c6a0f7a 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -200,14 +200,14 @@ void minusarch() {}
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
-// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha1,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
-// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
+// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha1,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
+// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha1,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" }
-// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha1,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha1,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
//.
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c b/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
index 269aec5ad0845..ad79eb4fcc02a 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
@@ -18,7 +18,8 @@
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
index bc5edbc77c9b9..35bf75ffff9d8 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
@@ -44,7 +44,8 @@
// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
index 3c20cff28821e..182f6e4d055b0 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
@@ -45,7 +45,8 @@
// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
index 444ac4526200f..b7c244cbb75fb 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
@@ -47,7 +47,8 @@
// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
index aa8cc7bd3badd..30484dbe9cf45 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
@@ -12,5 +12,6 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
index d219981e6be3c..de3d0c2dd55d1 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
@@ -17,6 +17,7 @@
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
index 27f066a310708..ec0c148ca649c 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
@@ -22,6 +22,7 @@
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
index 197b210259951..6aff96c291a67 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
@@ -32,7 +32,8 @@
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
index f1731ef034a0c..e5dd2f1dc1451 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
@@ -37,7 +37,8 @@
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
-// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA1 Enable SHA1 support
+// CHECK-NEXT: FEAT_SHA256 Enable SHA256 support
// CH...
[truncated]
|
8 tasks
|
I think you also need: |
|
I am abandoning this PR in favor of ARM-software/acle#347 |
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These features can be detected individually in Function Multiversioning therefore we would like to support them as separate features.