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[SelectionDAGBuilder][RISCV] Fix crash when using a memory constraint with scalable vector type. #99821

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Merged
merged 1 commit into from
Jul 22, 2024
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[SelectionDAGBuilder][RISCV] Fix crash when using a memory constraint with scalable vector type. #99821

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11 changes: 8 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9566,10 +9566,15 @@ static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
// Otherwise, create a stack slot and emit a store to it before the asm.
Type *Ty = OpVal->getType();
auto &DL = DAG.getDataLayout();
uint64_t TySize = DL.getTypeAllocSize(Ty);
TypeSize TySize = DL.getTypeAllocSize(Ty);
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo().CreateStackObject(
TySize, DL.getPrefTypeAlign(Ty), false);
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
int StackID = 0;
if (TySize.isScalable())
StackID = TFI->getStackIDForScalableVectors();
int SSFI = MF.getFrameInfo().CreateStackObject(TySize.getKnownMinValue(),
DL.getPrefTypeAlign(Ty), false,
nullptr, StackID);
SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL));
Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
MachinePointerInfo::getFixedStack(MF, SSFI),
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/pr99782.ll
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@@ -0,0 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel | FileCheck %s

define void @vslidedown() {
; CHECK-LABEL: name: vslidedown
; CHECK: bb.0.entry:
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.v, 0
; CHECK-NEXT: [[VL8RE8_V:%[0-9]+]]:vrm8 = VL8RE8_V killed [[ADDI]] :: (load (<vscale x 1 x s512>) from %ir.v, align 1)
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI %stack.1, 0
; CHECK-NEXT: VS8R_V killed [[VL8RE8_V]], killed [[ADDI1]] :: (store (<vscale x 1 x s512>) into %stack.1)
; CHECK-NEXT: INLINEASM &"vadd.vv $0, $0, $0", 25 /* sideeffect mayload maystore attdialect */, 262166 /* mem:m */, %stack.0.v, 0, 262166 /* mem:m */, %stack.1, 0
; CHECK-NEXT: PseudoRET
entry:
%v = alloca <vscale x 64 x i8>, align 1
%0 = load <vscale x 64 x i8>, ptr %v, align 1
call void asm sideeffect "vadd.vv $0, $0, $0", "=*imr,imr"(ptr elementtype(<vscale x 64 x i8>) %v, <vscale x 64 x i8> %0)
ret void
}