[topgen] Improve support for multiple address spaces

Individually generate C and Rust collateral for all address spaces

Signed-off-by: Robert Schilling <rschilling@rivosinc.com>

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -453,6 +453,7 @@
     {
       name: hart
       desc: The main address space, shared between the CPU and DM
+      default: true
       subspaces:
       [
         {

hw/top_darjeeling/data/top_darjeeling.hjson

@@ -181,6 +181,7 @@
   addr_spaces: [
     { name: "hart"
       desc: "The main address space, shared between the CPU and DM"
+      default: true
       subspaces: [
         { name: "mmio",
           desc: '''

hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_dbg_pkg.sv

@@ -0,0 +1,55 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \
+//                -o hw/top_darjeeling/ \
+//                --rnd_cnst_seed \
+//                1017106219537032642877583828875051302543807092889754935647094601236425074047
+
+package top_darjeeling_soc_dbg_pkg;
+  /**
+   * Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR = 32'h20000;
+
+  /**
+   * Peripheral size in bytes for dmi device on lc_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES = 32'h1000;
+
+  /**
+   * Peripheral base address for dbg device on rv_dm in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_RV_DM_DBG_BASE_ADDR = 32'h0;
+
+  /**
+   * Peripheral size in bytes for dbg device on rv_dm in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES = 32'h200;
+
+  /**
+   * Peripheral base address for soc device on mbx_jtag in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR = 32'h1000;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_jtag in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for jtag device on soc_dbg_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_SOC_DBG_CTRL_JTAG_BASE_ADDR = 32'h2300;
+
+  /**
+   * Peripheral size in bytes for jtag device on soc_dbg_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_SOC_DBG_CTRL_JTAG_SIZE_BYTES = 32'h20;
+
+
+endpackage

hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_mbx_pkg.sv

@@ -0,0 +1,105 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \
+//                -o hw/top_darjeeling/ \
+//                --rnd_cnst_seed \
+//                1017106219537032642877583828875051302543807092889754935647094601236425074047
+
+package top_darjeeling_soc_mbx_pkg;
+  /**
+   * Peripheral base address for soc device on mbx0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX0_SOC_BASE_ADDR = 32'h1465000;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX0_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX1_SOC_BASE_ADDR = 32'h1465100;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX1_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx2 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX2_SOC_BASE_ADDR = 32'h1465200;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx2 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX2_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx3 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX3_SOC_BASE_ADDR = 32'h1465300;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx3 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX3_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx4 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX4_SOC_BASE_ADDR = 32'h1465400;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx4 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX4_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx5 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX5_SOC_BASE_ADDR = 32'h1465500;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx5 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX5_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx6 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX6_SOC_BASE_ADDR = 32'h1465600;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx6 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX6_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR = 32'h1460100;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_pcie0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR = 32'h1460200;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_pcie1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES = 32'h20;
+
+
+endpackage

hw/top_darjeeling/sw/autogen/chip/mod.rs

@@ -3,3 +3,5 @@
 // SPDX-License-Identifier: Apache-2.0
 
 pub mod top_darjeeling;
+pub mod top_darjeeling_soc_dbg;
+pub mod top_darjeeling_soc_mbx;

hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs

@@ -21,6 +21,7 @@
 
 use core::convert::TryFrom;
 
+
 /// Peripheral base address for uart0 in top darjeeling.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped

hw/top_darjeeling/sw/autogen/top_darjeeling.c

@@ -120,7 +120,6 @@ const top_darjeeling_alert_peripheral_t
   [kTopDarjeelingAlertIdRvCoreIbexRecovHwErr] = kTopDarjeelingAlertPeripheralRvCoreIbex,
 };
 
-
 /**
  * PLIC Interrupt Source to Peripheral Map
  *

hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h

@@ -24,8 +24,6 @@
 
 // Include guard for assembler
 #ifdef __ASSEMBLER__
-
-
 /**
  * Memory base for soc_proxy_ctn in top darjeeling.
  */

hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.c

@@ -0,0 +1,10 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson
+// -o hw/top_darjeeling
+
+#include "hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.h"

hw/top_darjeeling/sw/autogen/top_darjeeling_soc_dbg.h

@@ -0,0 +1,112 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson
+// -o hw/top_darjeeling
+
+#ifndef OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_SOC_DBG_H_
+#define OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_SOC_DBG_H_
+
+/**
+ * @file
+ * @brief Top-specific Definitions
+ *
+ * This file contains preprocessor and type definitions for use within the
+ * device C/C++ codebase.
+ *
+ * These definitions are for information that depends on the top-specific chip
+ * configuration, which includes:
+ * - Device Memory Information (for Peripherals and Memory)
+ * - PLIC Interrupt ID Names and Source Mappings
+ * - Alert ID Names and Source Mappings
+ * - Pinmux Pin/Select Names
+ * - Power Manager Wakeups
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR 0x20000u
+
+/**
+ * Peripheral size for dmi device on lc_ctrl in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and
+ * `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for dbg device on rv_dm in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_RV_DM_DBG_BASE_ADDR 0x0u
+
+/**
+ * Peripheral size for dbg device on rv_dm in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and
+ * `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for soc device on mbx_jtag in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR 0x1000u
+
+/**
+ * Peripheral size for soc device on mbx_jtag in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and
+ * `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for jtag device on soc_dbg_ctrl in top darjeeling.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_DARJEELING_SOC_DBG_CTRL_JTAG_BASE_ADDR 0x2300u
+
+/**
+ * Peripheral size for jtag device on soc_dbg_ctrl in top darjeeling.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_DARJEELING_SOC_DBG_CTRL_JTAG_BASE_ADDR and
+ * `TOP_DARJEELING_SOC_DBG_CTRL_JTAG_BASE_ADDR + TOP_DARJEELING_SOC_DBG_CTRL_JTAG_SIZE_BYTES`.
+ */
+#define TOP_DARJEELING_SOC_DBG_CTRL_JTAG_SIZE_BYTES 0x20u
+
+
+
+// Header Extern Guard
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+
+#endif  // OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_SOC_DBG_H_