Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[spi_host/rtl] Fix sd_en_o of spi_host_fsm #24500

Merged
merged 1 commit into from
Sep 25, 2024
Merged

[spi_host/rtl] Fix sd_en_o of spi_host_fsm #24500

merged 1 commit into from
Sep 25, 2024

Conversation

andreaskurth
Copy link
Contributor

@andreaskurth andreaskurth commented Sep 3, 2024 •
edited by vogelpi
Loading

This reverts commit 7eb53da, which introduced a glitch on the sd_en_o output of spi_host_fsm.

This is not an ECO -- the ECO on the earlgrey_1.0.0 branch is in PR #24501. This PR makes the long-term fix to master.

This resolves #24631.

Regression Results

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.600m 200.000ms 49 50 98.00 %
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 16.689us 5 5 100.00 %
V1 csr_rw spi_host_csr_rw 4.000s 50.235us 20 20 100.00 %
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 59.435us 5 5 100.00 %
V1 csr_aliasing spi_host_csr_aliasing 4.000s 27.959us 5 5 100.00 %
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 78.979us 20 20 100.00 %
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 4.000s 50.235us 20 20 100.00 %
spi_host_csr_aliasing 4.000s 27.959us 5 5 100.00 %
V1 mem_walk spi_host_mem_walk 3.000s 14.666us 5 5 100.00 %
V1 mem_partial_access spi_host_mem_partial_access 3.000s 25.132us 5 5 100.00 %
V1 TOTAL 114 115 99.13 %
V2 performance spi_host_performance 8.000s 56.100us 50 50 100.00 %
V2 error_event_intr spi_host_overflow_underflow 1.667m 12.577ms 50 50 100.00 %
spi_host_error_cmd 8.000s 98.621us 50 50 100.00 %
spi_host_event 5.717m 27.495ms 50 50 100.00 %
V2 clock_rate spi_host_speed 19.000s 871.509us 50 50 100.00 %
V2 speed spi_host_speed 19.000s 871.509us 50 50 100.00 %
V2 chip_select_timing spi_host_speed 19.000s 871.509us 50 50 100.00 %
V2 sw_reset spi_host_sw_reset 9.750m 26.708ms 48 50 96.00 %
V2 passthrough_mode spi_host_passthrough_mode 6.000s 619.403us 50 50 100.00 %
V2 cpol_cpha spi_host_speed 19.000s 871.509us 50 50 100.00 %
V2 full_cycle spi_host_speed 19.000s 871.509us 50 50 100.00 %
V2 duplex spi_host_smoke 7.600m 200.000ms 49 50 98.00 %
V2 tx_rx_only spi_host_smoke 7.600m 200.000ms 49 50 98.00 %
V2 stress_all spi_host_stress_all 3.733m 10.001ms 49 50 98.00 %
V2 spien spi_host_spien 4.067m 29.288ms 50 50 100.00 %
V2 stall spi_host_status_stall 5.633m 30.109ms 46 50 92.00 %
V2 Idlecsbactive spi_host_idlecsbactive 41.000s 2.767ms 50 50 100.00 %
V2 data_fifo_status spi_host_overflow_underflow 1.667m 12.577ms 50 50 100.00 %
V2 alert_test spi_host_alert_test 4.000s 17.353us 50 50 100.00 %
V2 intr_test spi_host_intr_test 4.000s 31.076us 50 50 100.00 %
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 762.383us 20 20 100.00 %
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 762.383us 20 20 100.00 %
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 16.689us 5 5 100.00 %
spi_host_csr_rw 4.000s 50.235us 20 20 100.00 %
spi_host_csr_aliasing 4.000s 27.959us 5 5 100.00 %
spi_host_same_csr_outstanding 4.000s 114.409us 20 20 100.00 %
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 16.689us 5 5 100.00 %
spi_host_csr_rw 4.000s 50.235us 20 20 100.00 %
spi_host_csr_aliasing 4.000s 27.959us 5 5 100.00 %
spi_host_same_csr_outstanding 4.000s 114.409us 20 20 100.00 %
V2 TOTAL 683 690 98.99 %
V2S tl_intg_err spi_host_tl_intg_err 4.000s 56.058us 20 20 100.00 %
spi_host_sec_cm 4.000s 73.391us 5 5 100.00 %
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 56.058us 20 20 100.00 %
V2S TOTAL 25 25 100.00 %
Unmapped tests spi_host_upper_range_clkdiv 59.450m 100.003ms 4 10 40.00 %
TOTAL 826 840 98.33 %

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.00 % 90.89 % 83.13 % 92.75 % 89.76 % 95.70 % 100.00 % 95.22 % 90.87 %

Failure Buckets

  • UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 6 failures:
    • Test spi_host_upper_range_clkdiv has 5 failures.

      • 0.spi_host_upper_range_clkdiv.41767442353741875835931179648358720724892039760032609011138851629136922533015\
        Line 118, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

          UVM_FATAL @ 100001514930 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1caad1d4, Comparison=CompareOpEq, exp_data

=0x0, call_count=2)
UVM_INFO @ 100001514930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

    * 4.spi_host_upper_range_clkdiv.105328802617820497729064178320462039231596223485396510070516333560926321128713\                                                                   
      Line 154, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log                                                       
                                                                                                                                                                                      
            UVM_FATAL @ 100002964306 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x27a9aa94, Comparison=CompareOpEq, exp_data

=0x0, call_count=2)
UVM_INFO @ 100002964306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

    * ... and 3 more failures.                                                                                                                                                        
* Test spi_host_stress_all has 1 failures.                                                                                                                                            
    * 26.spi_host_stress_all.68155981691016775140114597463833196579857195204512793354880207130503226149626\                                                                           
      Line 154, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/26.spi_host_stress_all/latest/run.log                                                              
                                                                                                                                                                                      
            UVM_FATAL @ 10000912298 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf5ad3014, Comparison=CompareOpEq, exp_data=

0x0, call_count=2)
UVM_INFO @ 10000912298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

  • Job timed out after * minutes has 1 failures:

    • Test spi_host_upper_range_clkdiv has 1 failures.

      • 2.spi_host_upper_range_clkdiv.106191281816732251633055552225598218222312888967481446537200291588678511721240\
        Log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

          Job timed out after 60 minutes

  • UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=77) has 1 failures:

    • Test spi_host_status_stall has 1 failures.

      • 8.spi_host_status_stall.7976305311779925798410167447233672542085901160009957266227934868581453759047\
        Line 661, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log

          UVM_FATAL @ 10390175697 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xef0d36d4, Comparison=CompareOpEq, exp_data=0x

1, call_count=77)
UVM_INFO @ 10390175697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

  • UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
    • Test spi_host_sw_reset has 1 failures.

      • 10.spi_host_sw_reset.31922487595062807935629800711462886856678771030896593510817784284043776178055\
        Line 235, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log

          UVM_FATAL @ 10031274595 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc03fd114, Comparison=CompareOpEq, exp_data=

0x0, call_count=30)
UVM_INFO @ 10031274595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

  • UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=97) has 1 failures:

    • Test spi_host_status_stall has 1 failures.

      • 21.spi_host_status_stall.15523319771735123301902791637390013838533250398942658694464374721772107438078
        Line 769, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log

          UVM_FATAL @ 10637839343 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3ed219d4, Comparison=CompareOpEq, exp_data=0x1, call_count=97)
  UVM_INFO @ 10637839343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

  • UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=35) has 1 failures:

    • Test spi_host_sw_reset has 1 failures.

      • 22.spi_host_sw_reset.12520173052350117266462733467279026315518978058988191549369662463086310717325
        Line 243, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/22.spi_host_sw_reset/latest/run.log

          UVM_FATAL @ 10038590733 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x52514314, Comparison=CompareOpEq, exp_data=0x0, call_count=35)
  UVM_INFO @ 10038590733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

  • UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

    • Test spi_host_smoke has 1 failures.

      • 24.spi_host_smoke.87046963849190680649764514782609089628698015661253771763324272814076364208842
        Line 757, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/24.spi_host_smoke/latest/run.log

          UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

  • UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=86) has 1 failures:

    • Test spi_host_status_stall has 1 failures.

      • 40.spi_host_status_stall.51463953135159322352797777624573255486546398636443659054607011418224865465530
        Line 725, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log

          UVM_FATAL @ 52418697693 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa978a454, Comparison=CompareOpEq, exp_data=0x1, call_count=86)
  UVM_INFO @ 52418697693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

  • UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=82) has 1 failures:

    • Test spi_host_status_stall has 1 failures.

      • 43.spi_host_status_stall.51928236661722000903636025797588341102625815289564250533007755451431202482383
        Line 722, in log /home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log

          UVM_FATAL @ 26064179423 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd29a4514, Comparison=CompareOpEq, exp_data=0x1, call_count=82)
  UVM_INFO @ 26064179423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

INFO: [FlowCfg] [scratch_path]: [spi_host] [/home/dev/src/scratch/spi_host_fsm-fix/spi_host-sim-xcelium]
ERROR: [dvsim] Errors were encountered in this run.

      [   legend    ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]

00:00:29 [ build ]: [Q: 0, D: 0, P: 2, F: 0, K: 0, T: 2] 100%
01:41:58 [ run ]: [Q: 0, D: 0, P: 826, F: 13, K: 1, T: 840] 100%
01:42:07 [ cov_merge ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%
01:42:16 [ cov_report ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%

@andreaskurth andreaskurth added the ECO Accepted as an ECO label Sep 3, 2024
@andreaskurth andreaskurth self-assigned this Sep 3, 2024
@andreaskurth andreaskurth mentioned this pull request Sep 3, 2024
Merged
@andreaskurth andreaskurth marked this pull request as draft September 3, 2024 19:45
@hcallahan-lowrisc
Copy link
Contributor

This change looks correct to me, to remove the glitch potential on sd_en_o as described.

Minimal initial block-level testing (-i all -rx 0.1) doesn't show any problems from this change. I'm now running a full block-level regression and will post the results here (should be ready by the time CI has run through).

Thanks for running this full regression. I presume the results didn't raise any new breakage?

@andreaskurth
Copy link
Contributor Author

Thanks for running this full regression. I presume the results didn't raise any new breakage?

Correct; I've updated the PR description.

@andreaskurth andreaskurth removed the ECO Accepted as an ECO label Sep 5, 2024
@lowRISC lowRISC deleted a comment from moidx Sep 5, 2024
@andreaskurth andreaskurth marked this pull request as ready for review September 5, 2024 18:11
@andreaskurth
Copy link
Contributor Author

I changed this PR to no longer be an ECO but the proper / long-term fix on master. The ECO in PR #24501 is behaviorally equivalent, though, just keeps some unused wires and flops around to minimize the netlist diff.

@andreaskurth @vogelpi
Revert "[rtl, spi_host] spi_host_fsm fix"
661b833 
This reverts commit 7eb53da, which
introduced a glitch on the `sd_en_o` output of `spi_host_fsm`.

Signed-off-by: Andreas Kurth <adk@lowrisc.org>
@vogelpi
Copy link
Contributor

vogelpi commented Sep 24, 2024

Update: the ECO fix got confirmed by the PD team and the corresponding PR was merged in the release branch. I've now rebased this PR to retrigger CI and merge it afterwards.

@vogelpi
Copy link
Contributor

vogelpi commented Sep 24, 2024 •
edited
Loading

CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host_fsm.sv

This is an RTL change inline with the confirmed ECO (#24501).

vogelpi
vogelpi approved these changes Sep 24, 2024
View reviewed changes
Copy link
Contributor

@vogelpi vogelpi left a comment •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM, thanks @andreaskurth !

I've now triggered a block-level regression and will feed back the results here.

@andreaskurth andreaskurth mentioned this pull request Sep 24, 2024
Closed
@hcallahan-lowrisc
Copy link
Contributor

CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host_fsm.sv

RTL change to master which is a counterpart to the confirmed earlgrey_1.0.0 ECO (#24501).

@andreaskurth andreaskurth merged commit 620067f into lowRISC:master Sep 25, 2024
38 checks passed
@andreaskurth andreaskurth deleted the spi_host_fsm-fix branch September 25, 2024 11:15
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@vogelpi vogelpi vogelpi approved these changes

@hcallahan-lowrisc hcallahan-lowrisc hcallahan-lowrisc approved these changes

@a-will a-will Awaiting requested review from a-will

@moidx moidx Awaiting requested review from moidx

@OTshimeon OTshimeon Awaiting requested review from OTshimeon

@meisnere meisnere Awaiting requested review from meisnere

@antmarzam antmarzam Awaiting requested review from antmarzam

@arnonsha arnonsha Awaiting requested review from arnonsha

Assignees

@andreaskurth andreaskurth

Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.

[spi_host/rtl] Glitch on sd_en_o output
3 participants
@andreaskurth @hcallahan-lowrisc @vogelpi