Merge pull request #160 from braun-embedded/update-dependencies

Update dependencies
lpc-rs · Oct 11, 2019 · 1673554 · 1673554
2 parents f45a4be + d528658
commit 1673554
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Showing 19 changed files with 136 additions and 148 deletions.
diff --git a/.cargo/config b/.cargo/config
@@ -2,7 +2,7 @@
 target = "thumbv6m-none-eabi"
 
 [target.thumbv6m-none-eabi]
-runner = "arm-none-eabi-gdb"
+runner = "arm-none-eabi-gdb -tui -q -x openocd.gdb"
 rustflags = [
     # This parameter is duplicated in `scripts/build.sh`.
     # If needed, adjust it there as well.

diff --git a/lpc82x-hal/Cargo.toml b/lpc82x-hal/Cargo.toml
@@ -18,22 +18,22 @@ travis-ci = { repository = "lpc-rs/lpc8xx-hal" }
 
 
 [dependencies]
-cortex-m     = "0.5.2"
-embedded-hal = { version = "0.2", features = ["unproven"] }
-lpc82x-pac   = "0.6"
-nb           = "0.1.1"
-void         = { version = "1", default-features = false }
+cortex-m     = "0.6.1"
+embedded-hal = { version = "0.2.3", features = ["unproven"] }
+lpc82x-pac   = "0.7"
+nb           = "0.1.2"
+void         = { version = "1.0.2", default-features = false }
 # This should be in [dev-dependencies], but those can't be optional. Issue:
 # https://github.com/rust-lang/cargo/issues/1596
-compiletest_rs = { version = "0.3", optional = true }
+compiletest_rs = { version = "0.3.23", optional = true }
 
 [dependencies.lpc8xx-hal-common]
 path = "../lpc8xx-hal-common"
 version = "0.4.0"
 features = ["82x"]
 
 [dev-dependencies]
-cortex-m-rt = "0.6.3"
+cortex-m-rt = "0.6.10"
 panic-halt  = "0.2.0"
 
 

diff --git a/lpc82x-hal/examples/gpio.rs b/lpc82x-hal/examples/gpio.rs
@@ -54,8 +54,10 @@ fn main() -> ! {
 
     // Blink the LED
     loop {
+        #[allow(deprecated)]
         pio0_12.set_high();
         sleep.sleep(high_time);
+        #[allow(deprecated)]
         pio0_12.set_low();
         sleep.sleep(low_time);
     }

diff --git a/lpc82x-hal/examples/pmu.rs b/lpc82x-hal/examples/pmu.rs
@@ -73,6 +73,7 @@ fn main() -> ! {
         // `interrupt::free` will allow the interrupt to wake up the system, if
         // it's sleeping. But the interrupt handler won't run, which means we
         // don't have to define one.
+        #[allow(deprecated)]
         nvic.enable(Interrupt::WKT);
 
         // Busy Waiting

diff --git a/lpc82x-hal/.gdbinit → lpc82x-hal/openocd.gdb b/lpc82x-hal/.gdbinit → lpc82x-hal/openocd.gdb
@@ -1,4 +1,3 @@
-#set remotetimeout unlimited
 target remote | openocd
 load
 continue
diff --git a/lpc82x-hal/src/dma.rs b/lpc82x-hal/src/dma.rs
@@ -15,12 +15,14 @@ use crate::{
     init_state,
     raw::{
         self,
-        dma::{
+        dma0::{
             ACTIVE0,
-            CFG,
             ENABLESET0,
             SETTRIG0,
-            XFERCFG,
+            channel::{
+                CFG,
+                XFERCFG,
+            },
         },
     },
     reg_proxy::{
@@ -33,11 +35,11 @@ use crate::{
 
 /// Entry point to the DMA API
 pub struct DMA {
-    dma: raw::DMA,
+    dma: raw::DMA0,
 }
 
 impl DMA {
-    pub(crate) fn new(dma: raw::DMA) -> Self {
+    pub(crate) fn new(dma: raw::DMA0) -> Self {
         DMA { dma }
     }
 
@@ -67,7 +69,7 @@ impl DMA {
     /// prioritize it accordingly.
     ///
     /// [open an issue]: https://github.com/lpc-rs/lpc8xx-hal/issues
-    pub fn free(self) -> raw::DMA {
+    pub fn free(self) -> raw::DMA0 {
         self.dma
     }
 }
@@ -90,12 +92,12 @@ pub struct Parts {
 /// Handle to the DMA controller
 pub struct Handle<State = init_state::Enabled> {
     _state  : State,
-    dma     : raw::DMA,
+    dma     : raw::DMA0,
     srambase: u32,
 }
 
 impl Handle<init_state::Disabled> {
-    pub(crate) fn new(dma: raw::DMA, srambase: u32) -> Self {
+    pub(crate) fn new(dma: raw::DMA0, srambase: u32) -> Self {
         Handle {
             _state  : init_state::Disabled,
             dma     : dma,
@@ -276,7 +278,7 @@ impl<'dma, T> Channel<T, init_state::Enabled<&'dma Handle>>
             let w = w
                 .periphreqen().enabled()
                 .hwtrigen().disabled()
-                .trigburst().single_transfer();
+                .trigburst().single();
             unsafe { w.chpriority().bits(0) }
         });
 
@@ -286,12 +288,12 @@ impl<'dma, T> Channel<T, init_state::Enabled<&'dma Handle>>
             let w = w
                 .cfgvalid().valid()
                 .reload().disabled()
-                .swtrig().notset()
+                .swtrig().not_set()
                 .clrtrig().cleared()
                 .setinta().no_effect()
                 .setintb().no_effect()
-                .width()._8_bit_transfers_are()
-                .srcinc()._1_x_width()
+                .width().bit_8()
+                .srcinc().width_x_1()
                 .dstinc().no_increment();
             unsafe { w.xfercount().bits(source.len() as u16 - 1) }
         });
@@ -585,44 +587,44 @@ pub struct XFERCFG16;
 pub struct XFERCFG17;
 
 
-reg!(CFG0 , CFG, raw::DMA, cfg0 );
-reg!(CFG1 , CFG, raw::DMA, cfg1 );
-reg!(CFG2 , CFG, raw::DMA, cfg2 );
-reg!(CFG3 , CFG, raw::DMA, cfg3 );
-reg!(CFG4 , CFG, raw::DMA, cfg4 );
-reg!(CFG5 , CFG, raw::DMA, cfg5 );
-reg!(CFG6 , CFG, raw::DMA, cfg6 );
-reg!(CFG7 , CFG, raw::DMA, cfg7 );
-reg!(CFG8 , CFG, raw::DMA, cfg8 );
-reg!(CFG9 , CFG, raw::DMA, cfg9 );
-reg!(CFG10, CFG, raw::DMA, cfg10);
-reg!(CFG11, CFG, raw::DMA, cfg11);
-reg!(CFG12, CFG, raw::DMA, cfg12);
-reg!(CFG13, CFG, raw::DMA, cfg13);
-reg!(CFG14, CFG, raw::DMA, cfg14);
-reg!(CFG15, CFG, raw::DMA, cfg15);
-reg!(CFG16, CFG, raw::DMA, cfg16);
-reg!(CFG17, CFG, raw::DMA, cfg17);
-
-reg!(XFERCFG0 , XFERCFG, raw::DMA, xfercfg0 );
-reg!(XFERCFG1 , XFERCFG, raw::DMA, xfercfg1 );
-reg!(XFERCFG2 , XFERCFG, raw::DMA, xfercfg2 );
-reg!(XFERCFG3 , XFERCFG, raw::DMA, xfercfg3 );
-reg!(XFERCFG4 , XFERCFG, raw::DMA, xfercfg4 );
-reg!(XFERCFG5 , XFERCFG, raw::DMA, xfercfg5 );
-reg!(XFERCFG6 , XFERCFG, raw::DMA, xfercfg6 );
-reg!(XFERCFG7 , XFERCFG, raw::DMA, xfercfg7 );
-reg!(XFERCFG8 , XFERCFG, raw::DMA, xfercfg8 );
-reg!(XFERCFG9 , XFERCFG, raw::DMA, xfercfg9 );
-reg!(XFERCFG10, XFERCFG, raw::DMA, xfercfg10);
-reg!(XFERCFG11, XFERCFG, raw::DMA, xfercfg11);
-reg!(XFERCFG12, XFERCFG, raw::DMA, xfercfg12);
-reg!(XFERCFG13, XFERCFG, raw::DMA, xfercfg13);
-reg!(XFERCFG14, XFERCFG, raw::DMA, xfercfg14);
-reg!(XFERCFG15, XFERCFG, raw::DMA, xfercfg15);
-reg!(XFERCFG16, XFERCFG, raw::DMA, xfercfg16);
-reg!(XFERCFG17, XFERCFG, raw::DMA, xfercfg17);
-
-reg!(ACTIVE0   , ACTIVE0   , raw::DMA, active0   );
-reg!(ENABLESET0, ENABLESET0, raw::DMA, enableset0);
-reg!(SETTRIG0  , SETTRIG0  , raw::DMA, settrig0  );
+reg_cluster!(CFG0 , CFG, raw::DMA0, channel0,  cfg);
+reg_cluster!(CFG1 , CFG, raw::DMA0, channel1,  cfg);
+reg_cluster!(CFG2 , CFG, raw::DMA0, channel2,  cfg);
+reg_cluster!(CFG3 , CFG, raw::DMA0, channel3,  cfg);
+reg_cluster!(CFG4 , CFG, raw::DMA0, channel4,  cfg);
+reg_cluster!(CFG5 , CFG, raw::DMA0, channel5,  cfg);
+reg_cluster!(CFG6 , CFG, raw::DMA0, channel6,  cfg);
+reg_cluster!(CFG7 , CFG, raw::DMA0, channel7,  cfg);
+reg_cluster!(CFG8 , CFG, raw::DMA0, channel8,  cfg);
+reg_cluster!(CFG9 , CFG, raw::DMA0, channel9,  cfg);
+reg_cluster!(CFG10, CFG, raw::DMA0, channel10, cfg);
+reg_cluster!(CFG11, CFG, raw::DMA0, channel11, cfg);
+reg_cluster!(CFG12, CFG, raw::DMA0, channel12, cfg);
+reg_cluster!(CFG13, CFG, raw::DMA0, channel13, cfg);
+reg_cluster!(CFG14, CFG, raw::DMA0, channel14, cfg);
+reg_cluster!(CFG15, CFG, raw::DMA0, channel15, cfg);
+reg_cluster!(CFG16, CFG, raw::DMA0, channel16, cfg);
+reg_cluster!(CFG17, CFG, raw::DMA0, channel17, cfg);
+
+reg_cluster!(XFERCFG0 , XFERCFG, raw::DMA0, channel0,  xfercfg);
+reg_cluster!(XFERCFG1 , XFERCFG, raw::DMA0, channel1,  xfercfg);
+reg_cluster!(XFERCFG2 , XFERCFG, raw::DMA0, channel2,  xfercfg);
+reg_cluster!(XFERCFG3 , XFERCFG, raw::DMA0, channel3,  xfercfg);
+reg_cluster!(XFERCFG4 , XFERCFG, raw::DMA0, channel4,  xfercfg);
+reg_cluster!(XFERCFG5 , XFERCFG, raw::DMA0, channel5,  xfercfg);
+reg_cluster!(XFERCFG6 , XFERCFG, raw::DMA0, channel6,  xfercfg);
+reg_cluster!(XFERCFG7 , XFERCFG, raw::DMA0, channel7,  xfercfg);
+reg_cluster!(XFERCFG8 , XFERCFG, raw::DMA0, channel8,  xfercfg);
+reg_cluster!(XFERCFG9 , XFERCFG, raw::DMA0, channel9,  xfercfg);
+reg_cluster!(XFERCFG10, XFERCFG, raw::DMA0, channel10, xfercfg);
+reg_cluster!(XFERCFG11, XFERCFG, raw::DMA0, channel11, xfercfg);
+reg_cluster!(XFERCFG12, XFERCFG, raw::DMA0, channel12, xfercfg);
+reg_cluster!(XFERCFG13, XFERCFG, raw::DMA0, channel13, xfercfg);
+reg_cluster!(XFERCFG14, XFERCFG, raw::DMA0, channel14, xfercfg);
+reg_cluster!(XFERCFG15, XFERCFG, raw::DMA0, channel15, xfercfg);
+reg_cluster!(XFERCFG16, XFERCFG, raw::DMA0, channel16, xfercfg);
+reg_cluster!(XFERCFG17, XFERCFG, raw::DMA0, channel17, xfercfg);
+
+reg!(ACTIVE0   , ACTIVE0   , raw::DMA0, active0   );
+reg!(ENABLESET0, ENABLESET0, raw::DMA0, enableset0);
+reg!(SETTRIG0  , SETTRIG0  , raw::DMA0, settrig0  );
diff --git a/lpc82x-hal/src/lib.rs b/lpc82x-hal/src/lib.rs
@@ -217,14 +217,14 @@ pub struct Peripherals {
     /// A HAL API for this peripheral has not been implemented yet. In the
     /// meantime, this field provides you with the raw register mappings, which
     /// allow you full, unprotected access to the peripheral.
-    pub ADC: raw::ADC,
+    pub ADC: raw::ADC0,
 
     /// Analog comparator
     ///
     /// A HAL API for this peripheral has not been implemented yet. In the
     /// meantime, this field provides you with the raw register mappings, which
     /// allow you full, unprotected access to the peripheral.
-    pub CMP: raw::CMP,
+    pub CMP: raw::ACOMP,
 
     /// CRC engine
     ///
@@ -233,19 +233,12 @@ pub struct Peripherals {
     /// allow you full, unprotected access to the peripheral.
     pub CRC: raw::CRC,
 
-    /// DMA trigger mux
-    ///
-    /// A HAL API for this peripheral has not been implemented yet. In the
-    /// meantime, this field provides you with the raw register mappings, which
-    /// allow you full, unprotected access to the peripheral.
-    pub DMATRIGMUX: raw::DMATRIGMUX,
-
     /// Flash controller
     ///
     /// A HAL API for this peripheral has not been implemented yet. In the
     /// meantime, this field provides you with the raw register mappings, which
     /// allow you full, unprotected access to the peripheral.
-    pub FLASHCTRL: raw::FLASHCTRL,
+    pub FLASHCTRL: raw::FLASH_CTRL,
 
     /// I2C0-bus interface
     ///
@@ -287,21 +280,21 @@ pub struct Peripherals {
     /// A HAL API for this peripheral has not been implemented yet. In the
     /// meantime, this field provides you with the raw register mappings, which
     /// allow you full, unprotected access to the peripheral.
-    pub MRT: raw::MRT,
+    pub MRT: raw::MRT0,
 
     /// Pin interrupt and pattern match engine
     ///
     /// A HAL API for this peripheral has not been implemented yet. In the
     /// meantime, this field provides you with the raw register mappings, which
     /// allow you full, unprotected access to the peripheral.
-    pub PIN_INT: raw::PIN_INT,
+    pub PIN_INT: raw::PINT,
 
     /// State Configurable Timer (SCT)
     ///
     /// A HAL API for this peripheral has not been implemented yet. In the
     /// meantime, this field provides you with the raw register mappings, which
     /// allow you full, unprotected access to the peripheral.
-    pub SCT: raw::SCT,
+    pub SCT: raw::SCT0,
 
     /// SPI0
     ///
@@ -447,33 +440,32 @@ impl Peripherals {
     fn new(p: raw::Peripherals, cp: raw::CorePeripherals) -> Self {
         Peripherals {
             // HAL peripherals
-            DMA   : DMA::new(p.DMA),
+            DMA   : DMA::new(p.DMA0),
             // NOTE(unsafe) The init state of the gpio peripheral is enabled,
             // thus it's safe to create an already initialized gpio port
-            GPIO  : unsafe { GPIO::new_enabled(p.GPIO_PORT) },
+            GPIO  : unsafe { GPIO::new_enabled(p.GPIO) },
             I2C0  : I2C::new(p.I2C0),
             PMU   : PMU::new(p.PMU),
-            SWM   : SWM::new(p.SWM),
+            SWM   : SWM::new(p.SWM0),
             SYSCON: SYSCON::new(p.SYSCON),
             USART0: USART::new(p.USART0),
             USART1: USART::new(p.USART1),
             USART2: USART::new(p.USART2),
             WKT   : WKT::new(p.WKT),
 
             // Raw peripherals
-            ADC       : p.ADC,
-            CMP       : p.CMP,
+            ADC       : p.ADC0,
+            CMP       : p.ACOMP,
             CRC       : p.CRC,
-            DMATRIGMUX: p.DMATRIGMUX,
-            FLASHCTRL : p.FLASHCTRL,
+            FLASHCTRL : p.FLASH_CTRL,
             I2C1      : p.I2C1,
             I2C2      : p.I2C2,
             I2C3      : p.I2C3,
             INPUTMUX  : p.INPUTMUX,
             IOCON     : p.IOCON,
-            MRT       : p.MRT,
-            PIN_INT   : p.PIN_INT,
-            SCT       : p.SCT,
+            MRT       : p.MRT0,
+            PIN_INT   : p.PINT,
+            SCT       : p.SCT0,
             SPI0      : p.SPI0,
             SPI1      : p.SPI1,
             WWDT      : p.WWDT,

diff --git a/lpc82x-hal/src/reg_proxy.rs b/lpc82x-hal/src/reg_proxy.rs
@@ -103,3 +103,15 @@ macro_rules! reg {
         }
     }
 }
+
+macro_rules! reg_cluster {
+    ($ty:ident, $target:ty, $peripheral:path, $cluster:ident, $field:ident) => {
+        unsafe impl $crate::reg_proxy::Reg for $ty {
+            type Target = $target;
+
+            fn get() -> *const Self::Target {
+                unsafe { &(*<$peripheral>::ptr()).$cluster.$field as *const _ }
+            }
+        }
+    }
+}
diff --git a/lpc82x-hal/src/sleep.rs b/lpc82x-hal/src/sleep.rs
@@ -218,6 +218,7 @@ impl<'r, Clock> Sleep<Clock> for Regular<'r>
         // method can use the alarm flag, which would otherwise need to be reset
         // to exit the interrupt handler.
         interrupt::free(|_| {
+            #[allow(deprecated)]
             self.nvic.enable(Interrupt::WKT);
 
             while let Err(nb::Error::WouldBlock) = self.wkt.wait() {
@@ -226,6 +227,7 @@ impl<'r, Clock> Sleep<Clock> for Regular<'r>
 
             // If we don't do this, the (possibly non-existing) interrupt
             // handler will be called as soon as we exit this closure.
+            #[allow(deprecated)]
             self.nvic.disable(Interrupt::WKT);
         });
     }