sim: add module name to vcd (#225)

migen/sim/core.py

@@ -304,7 +304,7 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=
         if vcd_name is None:
             self.vcd = DummyVCDWriter()
         else:
-            self.vcd = VCDWriter(vcd_name)
+            self.vcd = VCDWriter(vcd_name, module_name=type(fragment_or_module).__name__)
 
             signals = list_signals(self.fragment)
             for cd in self.fragment.clock_domains:

migen/sim/vcd.py

@@ -19,8 +19,9 @@ def vcd_codes():
 
 
 class VCDWriter:
-    def __init__(self, filename):
+    def __init__(self, filename, module_name=None):
         self.filename = filename
+        self.module_name = module_name
         self.buffer_file = tempfile.TemporaryFile(
             dir=os.path.dirname(filename), mode="w+")
         self.codegen = vcd_codes()
@@ -72,6 +73,8 @@ def delay(self, delay):
     def close(self):
         out = open(self.filename, "w")
         try:
+            if self.module_name:
+                out.write("$scope module {name} $end\n".format(name=self.module_name))
             ns = build_namespace(self.codes.keys())
             for signal, code in self.codes.items():
                 name = ns.get_name(signal)
@@ -81,6 +84,8 @@ def close(self):
                     size = len(signal)
                 out.write("$var wire {size} {code} {name} $end\n"
                           .format(name=name, code=code, size=size))
+            if self.module_name:
+                out.write("$enddefinitions $end\n")
             out.write("$dumpvars\n")
             for signal in self.codes.keys():
                 self._write_value(out, signal, signal.reset.value)

migen/test/test_vcd.py

@@ -0,0 +1,44 @@
+import unittest
+import os
+import tempfile
+
+from migen.sim.vcd import VCDWriter
+
+
+class VcdWriter(unittest.TestCase):
+
+    def get_file_path(self, dir):
+        return os.path.join(dir, self.id() + ".vcd")
+
+    def check_expectation(self, filename, expectation):
+        self.vcd.close()
+        with open(filename, 'r') as f:
+            self.assertMultiLineEqual(expectation, f.read())
+
+    def test_empty(self):
+
+        expected_content = (
+            "$dumpvars\n"
+            "$end\n"
+            "#0\n"
+        )
+
+        with tempfile.TemporaryDirectory() as dir:
+            filename = self.get_file_path(dir)
+            self.vcd = VCDWriter(filename)
+            self.check_expectation(filename, expected_content)
+
+    def test_module_name(self):
+
+        expected_content = (
+            "$scope module name1 $end\n"
+            "$enddefinitions $end\n"
+            "$dumpvars\n"
+            "$end\n"
+            "#0\n"
+        )
+
+        with tempfile.TemporaryDirectory() as dir:
+            filename = self.get_file_path(dir)
+            self.vcd = VCDWriter(filename, module_name="name1")
+            self.check_expectation(filename, expected_content)