MIPS-Pipelining-Implementation

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This project, as the name suggests is an implementation of the MIPS pipelined processor.

This project is a part of our subject Computer Architecture And Microprocessors (CSN221) in the Indian Institute Of Technology, Roorkee.

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MIPS-Pipeline-Simulator

This program implement the simple MIPS pipeline, including the following instructions "lw", "sw", "add", "addi", "sub", "and", "andi", "or", "slt", "bne". In addition to the instructions, it also support detecting and dealing "data hazard", "hazard with load", "branch hazard".

Initialize

There are ten registers, and their initial value is as below:

The memory initial value is as below:

p.s. instruction memory is start from 0.

Input

The program will read the the input.txt file which in the same root, and the content of the file is the 32 bit machine codes. The format should like below.

10001101000000010000000000000011  
00000000000000100001100000100000  
00010000000000100000000000000110

The correspounding MIPS instructions is:

lw $1, 0x03($8)  
add $3, $0, $2  
beq $0, $2, 0x06 #(branch PC+4+4×6)   

Output

After executing the program, it will simulate every pipeline register's value on each clock cycle and saving the record as a .txt file named Result.

The content description: