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Experimental changes
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Merge & split 4->4 mode.
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@mar0x
mar0x committed Aug 10, 2022
1 parent a2ebfc4 commit 46574c8
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Showing 16 changed files with 1,153 additions and 649 deletions.
99 changes: 60 additions & 39 deletions firmware/midi-router-x2/midi.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
#include <midi.h>
#include <uart.h>
#include <crit_sec.h>
#include <splitter.h>

namespace {

Expand All @@ -13,79 +14,99 @@ using uart_c1 = uart_t<port::C1, 31250, rx_midi_traits<1>, tx_midi_traits<1> >;
template<> uart_c1::tx_ring_t uart_c1::tx_ring = {};
template<> uint8_t uart_c1::want_write = 0;

using UL = uart_list<uart_c0, uart_c1>;

midi::splitter_t<UL> splitter_state;

void splitter_rx_complete(uint8_t port, uint8_t data, bool ferr) {
splitter_state.rx_complete(port, data, ferr);
}

namespace midi {
void splitter_process_dre(uint8_t port) {
splitter_state.process_dre(port);
}

template<typename T>
inline void rx_complete() {
crit_sec cs;
bool ferr = T::ferr();
midi::on_rx_complete(T::rx_traits::id, T::data(), ferr);
}

template<typename T>
inline void process_bit() {
crit_sec cs;
splitter_state.process_bit(T::rx_traits::id, T::rx::read());
}

void init() {
PORTC.INT0MASK = 0;
PORTC.INTCTRL = 0;
template<typename T>
inline void process_dre() {
crit_sec cs;
T::on_dre_int();

uart_c0::setup();
uart_c1::setup();
midi::on_dre(T::rx_traits::id);
}

uart_c0::rxc_int_hi();
uart_c1::rxc_int_hi();
}

void splitter() {
uart_c0::disable();
uart_c1::disable();
namespace midi {

void init(process_byte_t cb) {
if (cb) {
splitter_state.disable();

uart_c0::port_traits::setup_pins();
uart_c1::port_traits::setup_pins();
on_rx_complete = cb;
on_dre = dummy_process_dre;
} else {
splitter_state.enable();

PORTC.INT0MASK = (1 << 2);
PORTC.INTCTRL = PORT_INT0LVL_HI_gc;
on_rx_complete = splitter_rx_complete;
on_dre = splitter_process_dre;
}
}

uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
switch (port) {
case 0: return uart_c0::write_buf(buf, size);
case 1: return uart_c1::write_buf(buf, size);
}
return UL::write_buf(port, buf, size);
}

void pending_timeout() {
splitter_state.pending_timeout();
}

return 0;
void dump_state() {
splitter_state.dump();
}

}


ISR(USARTC0_RXC_vect)
{
uart_c0::on_rxc_int();
rx_complete<uart_c0>();
}

ISR(USARTC0_DRE_vect)
{
uart_c0::on_dre_int();
process_dre<uart_c0>();
}

ISR(PORTC_INT0_vect)
{
process_bit<uart_c0>();
}


ISR(USARTC1_RXC_vect)
{
uart_c1::on_rxc_int();
rx_complete<uart_c1>();
}

ISR(USARTC1_DRE_vect)
{
uart_c1::on_dre_int();
process_dre<uart_c1>();
}


ISR(PORTC_INT0_vect)
ISR(PORTC_INT1_vect)
{
crit_sec cs;

bool v = uart_c0::rx::read();

if (v) {
uart_c0::tx::high();
uart_c1::tx::high();
} else {
uart_c0::tx::low();
uart_c1::tx::low();

midi::rx_ready = 1;
}
process_bit<uart_c1>();
}
130 changes: 74 additions & 56 deletions firmware/midi-router-x4-flat/midi.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
#include <midi.h>
#include <uart.h>
#include <crit_sec.h>
#include <splitter.h>

namespace {

Expand All @@ -21,114 +22,131 @@ using uart_e0 = uart_t<port::E0, 31250, rx_midi_traits<0>, tx_midi_traits<3> >;
template<> uart_e0::tx_ring_t uart_e0::tx_ring = {};
template<> uint8_t uart_e0::want_write = 0;

using UL = uart_list<uart_c0, uart_c1, uart_d0, uart_e0>;

midi::splitter_t<UL> splitter_state;

void splitter_rx_complete(uint8_t port, uint8_t data, bool ferr) {
splitter_state.rx_complete(port, data, ferr);
}

namespace midi {
void splitter_process_dre(uint8_t port) {
splitter_state.process_dre(port);
}

template<typename T>
inline void rx_complete() {
crit_sec cs;
bool ferr = T::ferr();
midi::on_rx_complete(T::rx_traits::id, T::data(), ferr);
}

void init() {
PORTE.INT0MASK = 0;
PORTE.INTCTRL = 0;
template<typename T>
inline void process_bit() {
crit_sec cs;
splitter_state.process_bit(T::rx_traits::id, T::rx::read());
}

uart_c0::setup();
uart_c1::setup();
uart_d0::setup();
uart_e0::setup();
template<typename T>
inline void process_dre() {
crit_sec cs;
T::on_dre_int();

uart_c0::rxc_int_hi();
uart_c1::rxc_int_hi();
uart_d0::rxc_int_hi();
uart_e0::rxc_int_hi();
midi::on_dre(T::rx_traits::id);
}

void splitter() {
uart_c0::disable();
uart_c1::disable();
uart_d0::disable();
uart_e0::disable();
}

namespace midi {

uart_c0::port_traits::setup_pins();
uart_c1::port_traits::setup_pins();
uart_d0::port_traits::setup_pins();
uart_e0::port_traits::setup_pins();
void init(process_byte_t cb) {
if (cb) {
splitter_state.disable();

on_rx_complete = cb;
on_dre = dummy_process_dre;
} else {
splitter_state.enable();

PORTE.INT0MASK = uart_e0::port_traits::rx::traits::bit_mask;
PORTE.INTCTRL = PORT_INT0LVL_HI_gc;
on_rx_complete = splitter_rx_complete;
on_dre = splitter_process_dre;
}
}

uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
switch (port) {
case 0: return uart_c0::write_buf(buf, size);
case 1: return uart_c1::write_buf(buf, size);
case 2: return uart_d0::write_buf(buf, size);
case 3: return uart_e0::write_buf(buf, size);
}
return UL::write_buf(port, buf, size);
}

return 0;
void pending_timeout() {
splitter_state.pending_timeout();
}

void dump_state() {
splitter_state.dump();
}

}


ISR(USARTC0_RXC_vect)
{
uart_c0::on_rxc_int();
rx_complete<uart_c0>();
}

ISR(USARTC0_DRE_vect)
{
uart_c0::on_dre_int();
process_dre<uart_c0>();
}

ISR(PORTC_INT0_vect)
{
process_bit<uart_c0>();
}


ISR(USARTC1_RXC_vect)
{
uart_c1::on_rxc_int();
rx_complete<uart_c1>();
}

ISR(USARTC1_DRE_vect)
{
uart_c1::on_dre_int();
process_dre<uart_c1>();
}

ISR(PORTC_INT1_vect)
{
process_bit<uart_c1>();
}


ISR(USARTD0_RXC_vect)
{
uart_d0::on_rxc_int();
rx_complete<uart_d0>();
}

ISR(USARTD0_DRE_vect)
{
uart_d0::on_dre_int();
process_dre<uart_d0>();
}

ISR(PORTE_INT0_vect)
ISR(PORTD_INT0_vect)
{
crit_sec cs;

bool v = uart_e0::rx::read();

if (v) {
uart_d0::tx::high();
uart_e0::tx::high();
uart_c0::tx::high();
uart_c1::tx::high();
} else {
uart_d0::tx::low();
uart_e0::tx::low();
uart_c0::tx::low();
uart_c1::tx::low();

midi::rx_ready = 1;
}
process_bit<uart_d0>();
}


ISR(USARTE0_RXC_vect)
{
uart_e0::on_rxc_int();
rx_complete<uart_e0>();
}

ISR(USARTE0_DRE_vect)
{
uart_e0::on_dre_int();
process_dre<uart_e0>();
}

ISR(PORTE_INT0_vect)
{
process_bit<uart_e0>();
}
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