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A MIPS32 5-Stage Pipeline CPU design from ground up. (for Spartan-3E Starter Kit Board)

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Name		Name	Last commit message	Last commit date
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coefiles		coefiles
includes		includes
src		src
ucf		ucf
.gitignore		.gitignore
Decode.vh		Decode.vh
LICENSE		LICENSE
README.md		README.md

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FiveStagePipeline

A MIPS32 5-Stage Pipeline CPU design from ground up.

Prefix

CS_ : Control Signal
PR_ : Pipeline Register
OP_ : MIPS Instruction
ALU_ : ALU Operation
FUNC_ : R-type Instruction func field
INST_TYPE_ : Just for display on LCD

planning to support those simple MIPS32 instructions

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A MIPS32 5-Stage Pipeline CPU design from ground up. (for Spartan-3E Starter Kit Board)

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