New x87 Unit Tests & Opcodes #184
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- FSTP Refactored and added Unit Tests - FSTSW Unit Tests - FSTCW Unit Tests - FCOMPP Fixes and Unit Tests
- FCOM added and added Unit Tests - FCOMP consolidated to call FCOM then Pop, added Unit Tests - FISTP added Unit Tests - FLD1 added Unit Tests - FST Refactored and added Unit Tests - FSTP Consolidated to call FST then Pop - FSQURT added edge-cases for FPU Exceptions and added Unit Tests - Added `ClearExceptions()` to the FPU Register to clear Exception Flags from both the Status Word and Control Word
…into x87-unit-tests
| var actualFPUCodes = mbbsEmuCpuRegisters.Fpu.StatusWord & FPU_CODE_MASK; | ||
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| Assert.Equal(expectedFlags, actualFPUCodes); | ||
| Assert.Equal(7, mbbsEmuCpuRegisters.Fpu.GetStackTop()); |
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popping 0 -> 7? Is that valid or one of those stack underflow exceptions which sets C1?
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It'd technically be a stack underflow. What'd happen on the next push is it pushes the value (ST0 == [0])
I don't set C1 or worry about those flags ATM because I haven't run across a module that verifies those values... yet 😉
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| namespace MBBSEmu.Tests.CPU | ||
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| public class FISTP_Tests : CpuTestBase |
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useful to add tests with different rounding modes as specified by the RC field in the FPU control word?
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Right now it's defaulting to rounding away from Zero. We can change it to respect the RC field eventually
| mbbsEmuCpuCore.FpuStack[1] = ST0Value; | ||
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| var instructions = new Assembler(16); | ||
| instructions.fstp(st1); |
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is there an assert that ST1 == ST0Value?
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In this test, ST1 becomes ST0 after the FSTP instruction because of the FPU POP. So we set the FPU Stack Top to [1], FSTP saves the result to ST1 [0] and the pop sets ST0 to [0].
MBBSEmu/CPU/CPUCore.cs
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| private void Op_Fsubrp() | ||
| { | ||
| var valueToSubtractFrom = GetOperandValueDouble(_currentInstruction.Op0Kind, EnumOperandType.Destination); | ||
| var valueToSubtract = GetOperandValueDouble(_currentInstruction.Op1Kind, EnumOperandType.Source); |
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FSUBR => (DST = SRC - DST)
At least with those EnumOperandTypes, it looks like DST - SRC. I don't really have all the context here, so just double check this is right
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Yeah -- this was backwards and a little confusing. I fixed the Unit Test to properly reflect subtracting destination (STi/1) from source (ST0). This is how Iced handles the disassembly of FSUBR. Where ST0 has to be the SOURCE operand.
Fixes #171