TCAM memory RTL generator v2.0

.pylintrc

@@ -4,7 +4,7 @@
 [C0303(trailing-whitespace)]
 disable=C0303
 
-# disable recommend using enumerate in for loops 
+# disable recommend using enumerate in for loops
 [C0200(consider-using-enumerate)]
 disable=C0200
 
@@ -16,10 +16,13 @@ disable=R0902
 [E1137(unsupported-assignment-operation)]
 disable=E1137
 
-# diable unsubscriptable object 
+# disable unsubscriptable object
 [E1136(unsubscriptable-object)]
 disable=E1136
 
+# disable no-member
+[E1101(no-member)]
+disable=E1101
 
 # =======================================================================================
 # =======================================================================================
@@ -67,7 +70,7 @@ max-public-methods=20
 # Maximum number of return / yield for function / method body.
 max-returns=5
 # Maximum number of statements in function / method body.
-max-statements=50
+max-statements=100
 # Minimum number of public methods for a class (see R0903).
 min-public-methods=2
 

.vscode/extensions.json

@@ -12,7 +12,6 @@
         "ms-python.vscode-pylance",
         "ms-python.python",
         "kevinrose.vsc-python-indent",
-        "mshr-h.systemverilog",
         "mshr-h.veriloghdl",
         "redhat.vscode-yaml"
     ]

.vscode/settings.json

@@ -1,6 +1,11 @@
 {
+    // only change these settings as you prefer
+    "editor.fontSize": 13,
+    "terminal.integrated.fontSize": 13,
+    "editor.fontFamily": "'CaskaydiaCove Nerd Font Mono'",
+    "terminal.integrated.fontFamily": "CaskaydiaCove Nerd Font Mono",
+    // dont change these settings
     "python.defaultInterpreterPath": ".pyVenvOpenTcam/bin/python",
-    "editor.fontSize": 12,
     "editor.tabSize": 4,
     "editor.insertSpaces": true,
     "editor.bracketPairColorization.enabled": true,
@@ -9,10 +14,9 @@
     "editor.detectIndentation": true,
     "editor.lineHeight": 0,
     "editor.minimap.enabled": false,
-    "terminal.integrated.fontSize": 11,
     "terminal.integrated.lineHeight": 1,
     "terminal.integrated.shellIntegration.enabled": true,
-    // "files.trimTrailingWhitespace": true,
+    "files.trimTrailingWhitespace": true,
     "markdown.preview.fontSize": 10,
     "markdown.preview.lineHeight": 1.0,
     "markdown-preview-github-styles.colorTheme": "light",
@@ -26,10 +30,14 @@
     "cSpell.enabled": true,
     "cSpell.caseSensitive": true,
     "cSpell.words": [
+        "combinational",
         "damerau",
+        "dataframe",
         "levenshtein",
-        "tcam", "TCAM",
-        "sram", "SRAM",
-        "dataframe"
+        "sram",
+        "SRAM",
+        "tcam",
+        "TCAM",
+        "verilog"
     ]
 }

Makefile

@@ -99,34 +99,32 @@ run_coverage:
 gen_apidocs:
 	@ echo " "
 	@ echo ------------------------ OpenTCAM API Documentation ------------------------
-	@ pdoc ./compiler/src/tableMapping.py -o ${DIR_DOCS}
+	@ pdoc ./compiler/src/*.py -o ${DIR_DOCS}
 	@ echo ------------------------------------ DONE ----------------------------------
 	@ echo " "
 
 run_pylint:
 	@ echo " "
 	@ echo ------------------------------ Running PyLint ------------------------------
 	@ [ -d ${DIR_LOGS} ] || mkdir -p ${DIR_LOGS}
-	@ pylint ${DIR_COMP_SRC}/mainTableMapping.py \
+	@ pylint ${DIR_COMP_SRC}/*.py \
 	--output-format=${FORMAT}:./logs/pylint.log,${COLOR} \
 	--score=${SCORE} --reports=${REPORTS} \
 	--rcfile=.pylintrc
 	@ echo ------------------------------------ DONE ----------------------------------
 	@ echo " "
 
-# @ pylint ${DIR_COMP_SRC}/*.py \
-
 run_isort:
 	@ echo " "
 	@ echo ------------------------------ Running iSort ------------------------------
-	@ isort -v compiler/src/mainTableMapping.py
+	@ isort -v compiler/src/*.py
 	@ echo ------------------------------------ DONE ----------------------------------
 	@ echo " "
 
 run_black:
 	@ echo " "
 	@ echo ------------------------------ Running Black ------------------------------
-	@ black -v compiler/src/mainTableMapping.py
+	@ black -v compiler/src/*.py
 	@ echo ---------------------------------- DONE -----------------------------------
 	@ echo " "
 
@@ -196,7 +194,7 @@ clean_coverage:
 	@ echo ------------------------------------ DONE ----------------------------------
 	@ echo " "
 
-clean_all: 
+clean_all:
 	@ make clean_logs clean_sramtablemap clean_tcamrtl clean_tests clean_coverage clean_apidocs
 
 deepclean:
@@ -229,7 +227,7 @@ help:
 	@ echo " "
 	@ echo " tcamrtl:			generate TCAM memory RTL wrapper"
 	@ echo "	TCAMWRAPCONFIG=tcamMemWrapper_XxY	tcam memory config name"
-	@ echo "	TIMEUNIT=1ns				set timeunit resolution" 
+	@ echo "	TIMEUNIT=1ns				set timeunit resolution"
 	@ echo "	TIMEPRECISION=1ps			set timeprecision resolution"
 	@ echo "	DEBUG=1/0				debugging on/off"
 	@ echo "	VERBOSE=1/0				verbosity on/off"

compiler/src/andGate.py

@@ -0,0 +1,106 @@
+"""
+List of all pip packages imported
+"""
+
+import logging
+import os
+
+from migen import *
+from migen.fhdl.verilog import convert
+
+# ===========================================================================================
+# ======================================= Begin Class =======================================
+# ===========================================================================================
+
+
+class AndGate(Module):
+    """
+    Generates the verilog code for an AND gate with N inputs each input M bits wide.
+    The output is M bits wide.
+    """
+
+    # * ----------------------------------------------------------------- Variables
+    def __init__(self, inputPorts, dataWidth):
+        """
+        Constructor: call IO ports and logic here
+
+        **Public Variables:**
+        :param list inputs          list containing objects for all input ports.
+        :param list outputs         list containing objects for all output ports.
+        :param int inputPorts:      number of input ports.
+        :param int dataWidth:       width of input ports.
+        :return str verilogCode:    store RTL code of the gate.
+        """
+        # * variables
+        self.numInputs = inputPorts
+        self.numInputWidth = dataWidth
+        self.verilogCode = ""
+
+        # * signals
+        self.inputs = []
+        self.outputs = []
+
+        # * setup IO ports
+        self.ioPorts()
+        # * generate block RTL
+        self.logicBlock()
+
+    def ioPorts(self):
+        """
+        Create a list of Signal objects for N input ports each of width M. Create a Signal object for an output port of width M.
+        """
+        for port in range(self.numInputs):
+            tempPort = Signal(self.numInputWidth, name_override=f"in_data{port}")
+            self.inputs.append(tempPort)
+            logging.info("Created AND gate input port: in_data%d[%d:%d]", port, self.numInputWidth - 1, 0)
+        self.outputs = Signal(self.numInputWidth, name_override="out_data")
+        logging.info("Created AND gate output port: out_data%d[%d:%d]", port, self.numInputWidth - 1, 0)
+
+    def logicBlock(self):
+        """
+        Setup the combinatorial logic for creating an AND gate using migen.
+        Using the reduce() function to combine all input signals into a single output signal.
+        """
+        self.comb += self.outputs.eq(reduce(lambda x, y: x & y, self.inputs))
+        logging.info("Generated AND gate logic")
+
+
+# ===========================================================================================
+# ======================================== End Class ========================================
+# ===========================================================================================
+
+
+def genVerilogAndGate(inputPorts, dataWidth, filePath):
+    """
+    Main user function for class andGate.
+    Creates the IO ports for the verilog RTL module definition.
+    Generates the verilog code for an AND gate with N inputs each input M bits wide. The output is M bits wide.
+
+    :param int inputPorts:      number of input ports.
+    :param int dataWidth:       width of input ports.
+    :param str filePath:        absolute path for the verilog file.
+    :return str:                RTL code of the gate.
+    """
+    # * instantiate the module
+    gate = AndGate(inputPorts=inputPorts, dataWidth=dataWidth)
+
+    # * ----- setup the IO ports for the verilog module definition
+    # * input port set
+    inPortsSet = {gate.inputs[i] for i in range(inputPorts)}
+    # * output port set
+    outPortsSet = {gate.outputs}
+    # * combine input and output sets
+    moduleIOs = inPortsSet.union(outPortsSet)
+    logging.info("Generated AND gate verilog module definition")
+
+    # * generate the verilog code
+    moduleName = os.path.basename(filePath).replace(".sv", "")
+    gate.verilogCode = convert(gate, name=moduleName, ios=moduleIOs)
+    logging.info("Generated AND gate verilog module RTL")
+
+    # * write verilog code to a file
+    with open(filePath, "w", encoding="utf-8") as rtl:
+        rtl.write(str(gate.verilogCode))
+    logging.info('Created rtl file "%s"', filePath)
+
+    return str(gate.verilogCode)

compiler/src/mainTcamMemTopWrapper.py

@@ -0,0 +1,111 @@
+"""
+List of all pip packages imported
+"""
+import argparse
+import logging
+import os
+import shutil
+import sys
+
+from andGate import *
+from priorityEncoder import *
+from tcamMemBlock7x64 import *
+from tcamMemTopWrapper import *
+
+
+def main():
+    """
+    main func for implementing py class TcamMemTopWrapper
+    """
+    # * ----- variables
+    pwd = os.getcwd()
+    logsDirPath = ""
+    tcamRtlDirPath = ""
+    tcamRtlConfigDirPath = ""
+    rtlFilePath = ""
+    memLength = 0
+    memWidth = 0
+    pathSram1kb = "compiler/lib/tcam_block_rtl/sky130_sram_1kbyte_1rw1r_32x256_8.sv"
+
+    # create logs dir if it doesn't exist
+    logsDirPath = os.path.join(pwd, "logs")
+    if os.path.exists(logsDirPath) is False:
+        os.makedirs("logs")
+    # create rtl dir if it doesn't exist
+    tcamRtlDirPath = os.path.join(pwd, "tcam_mem_rtl")
+    if os.path.exists(tcamRtlDirPath) is False:
+        os.makedirs("tcam_mem_rtl")
+    # logging config
+    logging.basicConfig(
+        level=logging.DEBUG,
+        filename="./logs/tcamMemoryWrapper.log",
+        format="%(asctime)s | %(filename)s | %(funcName)s | %(levelname)s | %(lineno)d | %(message)s",
+    )
+
+    # set arguments for OpenTCAM RTL memory generator
+    parser = argparse.ArgumentParser(
+        prog="OpenTCAM",
+        usage="%(prog)s [options] path",
+        description="TCAM memory generator",
+        epilog="Python framework for generating configurable SRAM based TCAM memories",
+    )
+    # list of all possible args for OpenTCAM
+    parser.add_argument(
+        "-conf", "--tcamConfig", type=str, default="tcam_64x28", metavar="", required=True, nargs="?", help="name of specific TCAM mem wrapper config"
+    )
+    parser.add_argument("-d", "--debug", type=int, default=0, metavar="", required=False, nargs="?", help="print debugging mode")
+    parser.add_argument("-v", "--verbose", type=int, default=0, metavar="", required=False, nargs="?", help="print verbose mode")
+    arg = parser.parse_args()
+
+    # ====================================================== code main body
+
+    # * calculate how many tcam block are required
+    if arg.tcamConfig:
+        memLength = int(arg.tcamConfig[5:7])
+        memWidth = int(arg.tcamConfig[8:10])
+        if (memLength == 64) and (memWidth % 7 == 0):
+            print('"VALID" TCAM memory wrapper config. tcam_[64]x[7*N] == %s\n', arg.tcamConfig)
+            logging.info('"VALID" TCAM memory wrapper config. tcam_[64]x[7*N] == %s', arg.tcamConfig)
+            logging.info("Total TCAM memory 64x7 blocks required: %d", int(memWidth / 7))
+            # * create rtl dir for specific tcam mem wrap config
+            tcamRtlConfigDirPath = os.path.join(tcamRtlDirPath, arg.tcamConfig)
+            if os.path.exists(tcamRtlConfigDirPath):
+                shutil.rmtree(tcamRtlConfigDirPath)
+            os.makedirs(tcamRtlConfigDirPath)
+            logging.info("Created TCAM memory RTL dir: %s", tcamRtlConfigDirPath)
+            # * copy sky130 block to required config dir
+            shutil.copy(pathSram1kb, tcamRtlConfigDirPath)
+            logging.info('Copied file "%s" to dir "%s"', pathSram1kb, tcamRtlConfigDirPath)
+            print('Copied rtl file "%s" to dir "%s"', os.path.basename(pathSram1kb), tcamRtlConfigDirPath)
+            # * generate verilog for TCAM memory MxN top wrapper
+            fileName = "top_tcam_mem_" + str(memLength) + "x" + str(memWidth) + ".sv"
+            rtlFilePath = os.path.join(tcamRtlConfigDirPath, fileName)
+            codeTcamMemTopWrapper = genVerilogTcamMemTopWrapper(memBlocks=int(memWidth / 7), filePath=rtlFilePath)
+            print('Created rtl file: "%s"', rtlFilePath)
+            if arg.debug:
+                print(codeTcamMemTopWrapper)
+            # * generate verilog for TCAM memory block 7x64
+            rtlFilePath = os.path.join(tcamRtlConfigDirPath, "tcam_mem_7x64.sv")
+            codeTcamMemBlock7x64 = genVerilogTcamMemBlock7x64(filePath=rtlFilePath)
+            print('Created rtl file: "%s"', rtlFilePath)
+            if arg.debug:
+                print(codeTcamMemBlock7x64)
+            # * generate verilog for andgate
+            rtlFilePath = os.path.join(tcamRtlConfigDirPath, "and_gate.sv")
+            codeAndGate = genVerilogAndGate(inputPorts=2, dataWidth=64, filePath=rtlFilePath)
+            print('Created rtl file: "%s"', rtlFilePath)
+            if arg.debug:
+                print(codeAndGate)
+            # * generate verilog for priority encoder
+            rtlFilePath = os.path.join(tcamRtlConfigDirPath, "priority_encoder_64x6.sv")
+            codePriorityEncoder = genVerilogPriorityEncoder(inDataWidth=64, filePath=rtlFilePath)
+            print('Created rtl file: "%s"', rtlFilePath)
+            if arg.debug:
+                print(codePriorityEncoder)
+        else:
+            logging.info('"INVALID" TCAM memory wrapper config. tcam_[64]x[7*N] != %s', arg.tcamConfig)
+            sys.exit('"INVALID" TCAM memory wrapper config. tcam_[64]x[7*N] != %s', arg.tcamConfig)
+
+
+if __name__ == "__main__":
+    main()

compiler/src/mainTcamRTLGenerator.py

@@ -1,7 +1,7 @@
-from tcamRtlGenerator import * 
+from tcamRtlGenerator import *
 import argparse
 import os
-os.system('clear')
+# os.system('clear')
 
 def new_main():
     # create logs dir if it doesnt exist
@@ -32,12 +32,12 @@ def new_main():
     parser.add_argument('-v','--verbose',
                         type=int,default=0,metavar='',required=False,nargs='?',help='print verbose mode')
     arg = parser.parse_args()
-    
-    # ====================================================== code main body    
-    
+
+    # ====================================================== code main body
+
     # class objects
     trwg1=TcamRtlWrapperGenerator()
-    
+
     # get project dir
     trwg1.getPrjDir(arg.verbose)
     # get tcam table config yaml file path