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generator: add generation of unsigned immediates
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OleksiiOleksenko committed Apr 16, 2024
1 parent 493d347 commit a416218
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Showing 5 changed files with 30 additions and 338 deletions.
37 changes: 24 additions & 13 deletions src/generator.py
Original file line number Diff line number Diff line change
Expand Up @@ -498,21 +498,32 @@ def generate_mem_operand(self, spec: OperandSpec, _: Instruction) -> Operand:
return MemoryOperand(address_reg, spec.width, spec.src, spec.dest)

def generate_imm_operand(self, spec: OperandSpec, _: Instruction) -> Operand:
# generate bitmask
if spec.values and spec.values[0] == "bitmask":
# FIXME: this implementation always returns the same bitmask
# make it random
value = str(pow(2, spec.width) - 2)
return ImmediateOperand(value, spec.width)

# generate from a predefined range
if spec.values:
if spec.values[0] == "bitmask":
# FIXME: this implementation always returns the same bitmask
# make it random
value = str(pow(2, spec.width) - 2)
else:
assert "[" in spec.values[0], spec.values
range_ = spec.values[0][1:-1].split("-")
if range_[0] == "":
range_ = range_[1:]
range_[0] = "-" + range_[0]
assert len(range_) == 2
value = str(random.randint(int(range_[0]), int(range_[1])))
assert "[" in spec.values[0], spec.values
range_ = spec.values[0][1:-1].split("-")
if range_[0] == "":
range_ = range_[1:]
range_[0] = "-" + range_[0]
assert len(range_) == 2
value = str(random.randint(int(range_[0]), int(range_[1])))
ImmediateOperand(value, spec.width)

# generate from width
if spec.signed:
range_min = pow(2, spec.width - 1) * -1
range_max = pow(2, spec.width - 1) - 1
else:
value = str(random.randint(pow(2, spec.width - 1) * -1, pow(2, spec.width - 1) - 1))
range_min = 0
range_max = pow(2, spec.width) - 1
value = str(random.randint(range_min, range_max))
return ImmediateOperand(value, spec.width)

def generate_label_operand(self, spec: OperandSpec, parent: Instruction) -> Operand:
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1 change: 1 addition & 0 deletions src/interfaces.py
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ class OperandSpec:
values: List[str]
type: OT
width: int
signed: bool = True
src: bool
dest: bool

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1 change: 1 addition & 0 deletions src/isa_loader.py
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@ def parse_operand(self, op: Dict, parent: InstructionSpec) -> OperandSpec:
op_values = sorted(op_values)
spec = OperandSpec(op_values, op_type, op["src"], op["dest"])
spec.width = op["width"]
spec.signed = op.get("signed", True)

if op_type == OT.MEM:
parent.has_mem_operand = True
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5 changes: 4 additions & 1 deletion src/x86/get_spec.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ class OperandSpec:
values: List[str]
type_: str
width: int
signed: bool = True
comment: str
src: bool = False
dest: bool = False
Expand Down Expand Up @@ -217,6 +218,8 @@ def parse_imm_operand(op):
spec.src = True
spec.dest = False
spec.width = int(op.attrib.get('width'))
if op.attrib.get('s', '1') == '0':
spec.signed = False
return spec

@staticmethod
Expand Down Expand Up @@ -304,7 +307,7 @@ def __init__(self, extensions: List[str], out_file: str) -> None:
def run(self):
subprocess.run(
"wget "
"https://github.com/microsoft/sca-fuzzer/releases/download/v1.2/x86_instructions.xml",
"https://github.com/microsoft/sca-fuzzer/releases/download/v1.2.4/x86_instructions.xml",
shell=True,
check=True)

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