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This is a 6 Stage Pipelined single-core CPU built on Harvard Architecture in VHDL.

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Assembler
Assembler
 
 
ALU.vhd
ALU.vhd
 
 
Branch.vhd
Branch.vhd
 
 
Branching.do
Branching.do
 
 
CCR.vhd
CCR.vhd
 
 
CallRet.mem
CallRet.mem
 
 
Calldo.txt
Calldo.txt
 
 
ControllerUnit.vhd
ControllerUnit.vhd
 
 
DataMemory.vhd
DataMemory.vhd
 
 
Datamemory.do
Datamemory.do
 
 
Decode.vhd
Decode.vhd
 
 
Execute.vhd
Execute.vhd
 
 
HazardCounter.vhd
HazardCounter.vhd
 
 
HazardDetectionUnit.vhd
HazardDetectionUnit.vhd
 
 
Integration.vhd
Integration.vhd
 
 
MemoryTest.mem
MemoryTest.mem
 
 
PC.vhd
PC.vhd
 
 
Phase3Waveform.do
Phase3Waveform.do
 
 
Processor.vhd
Processor.vhd
 
 
README.md
README.md
 
 
Register.vhd
Register.vhd
 
 
Register11.vhd
Register11.vhd
 
 
RegistersFile.vhd
RegistersFile.vhd
 
 
RegistersWithVec.vhd
RegistersWithVec.vhd
 
 
SP.do
SP.do
 
 
SP.vhd
SP.vhd
 
 
Trial.do
Trial.do
 
 
WriteBackMux.vhd
WriteBackMux.vhd
 
 
execute.do
execute.do
 
 
fetch.do
fetch.do
 
 
fetch.vhd
fetch.vhd
 
 
forwardingUnit.vhd
forwardingUnit.vhd
 
 
inst.mem
inst.mem
 
 
instruction_cache.vhd
instruction_cache.vhd
 
 
integ.do
integ.do
 
 
integration.mem
integration.mem
 
 
interruptLatch.vhd
interruptLatch.vhd
 
 
jump.mem
jump.mem
 
 
logo.gif
logo.gif
 
 
mux16.vhd
mux16.vhd
 
 
mux2.vhd
mux2.vhd
 
 
mux4.vhd
mux4.vhd
 
 
mux8.vhd
mux8.vhd
 
 
my_adder.vhd
my_adder.vhd
 
 
my_nadder.vhd
my_nadder.vhd
 
 
operandLatch.vhd
operandLatch.vhd
 
 
select_adder.vhd
select_adder.vhd
 
 
test.do
test.do
 
 
testcases.mem
testcases.mem
 
 
testcases2.do
testcases2.do
 
 
testcases2.mem
testcases2.mem
 
 

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6 Stage Processor

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Table of Contents

Project Description

A 6-Stage Digital Processor that works on Harvard Architecture utilizing Full Forwarding and Branch Prediction to improve performance. An assembler was also custom designed to suit our instruction set.

Final Design

6StageProcessor drawio

How to use

  1. Create a project using modelsim and add all vhdl files.
  2. Compile all files.
  3. Run Assembler.cpp on your desired code.
  4. Copy any do file and edit the memory importing command and any intializations.
  5. Run your do file and Watch your code in action.

References

You can find more about the project specifics in the project document and reference textbook.

Contributors

  1. Mohammed Tarek AbdElmohsen
  2. Mahmoud Samy
  3. Ahmed Yasser
  4. Mina Ashraf

About

This is a 6 Stage Pipelined single-core CPU built on Harvard Architecture in VHDL.

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  • Stata 72.1%
  • VHDL 18.2%
  • C++ 9.7%