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Add support for AVX512 Vpclmulqdq, Vbmi2, Vnni, & Vaes instructions #349
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Codecov Report
@@ Coverage Diff @@
## master #349 +/- ##
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+ Coverage 75.92% 75.98% +0.06%
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Files 65 65
Lines 20694 21014 +320
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+ Hits 15711 15967 +256
- Misses 4901 4965 +64
Partials 82 82
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This is awesome! Going to take these one-by-one and land them independently. VAES just landed in #358. |
It was possible to substantially simplify the VNNI instruction list, see #359. AVX-512 instruction form expansion for masking/zeroing/broadcast versions is applied to the lists in Not sure yet whether these simplifications will be possible for the other ISAs. |
Adds VEX and EVEX encoded versions of the `PCLMULQDQ` carry-less quadword multiplication instruction. These are added via the `opcodesextra` mechanism #345, since they're missing from the opcodes database. Contributed by @vsivsi. Extracted from #349 with minor tweaks. Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
Adds the "Vector Bit Manipulation Instructions 2" instruction set. These new instructions are added via the `opcodesextra` mechanism #345, since they're missing from the opcodes database. Contributed by @vsivsi. Extracted from #349 with simplifications. Specifically, as prompted by the `dupl` linter we extract some common forms lists into a helper `forms.go` file. Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
This PR, in conjunction with #234, rounds out the "missing" AVX512 extensions which are supported by the Golang assembler, but not present in the
X86_64.xml
file used to generate Avo's instruction support files.With the addition of the instructions in these two PRs (plus those merged in #344), Avo will support all of the AVX512 instructions up through the Intel Sunny Cove (Ice & Rocket Lake) and AMD Zen4 processor lines.
Instructions were added using the same
opcodesextra
mechanism as was used in the GFNI PR.