[fiber] Align fiber namespace and functions with std naming

- modm::fiber -> modm::this_fiber. - modm::fiber::sleep() -> modm::this_fiber::sleep_for().
modm-io · Apr 20, 2024 · 1b27b3c · 1b27b3c
1 parent 78b2e26
commit 1b27b3c
Show file tree

Hide file tree

Showing 28 changed files with 90 additions and 70 deletions.
diff --git a/examples/avr/fiber/main.cpp b/examples/avr/fiber/main.cpp
@@ -24,14 +24,14 @@ void
 fiber_function1()
 {
 	MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-	while (++f1counter < cycles) { modm::fiber::yield(); total_counter++; }
+	while (++f1counter < cycles) { modm::this_fiber::yield(); total_counter++; }
 }
 
 void
 fiber_function2(uint32_t cyc)
 {
 	MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-	while (++f2counter < cyc) { modm::fiber::yield(); total_counter++; }
+	while (++f2counter < cyc) { modm::this_fiber::yield(); total_counter++; }
 }
 
 struct Test
@@ -40,14 +40,14 @@ struct Test
 	fiber_function3()
 	{
 		MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-		while (++f3counter < cycles) { modm::fiber::yield(); total_counter++; }
+		while (++f3counter < cycles) { modm::this_fiber::yield(); total_counter++; }
 	}
 
 	void
 	fiber_function4(uint32_t cyc)
 	{
 		MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-		while (++f4counter < cyc) { modm::fiber::yield(); total_counter++; }
+		while (++f4counter < cyc) { modm::this_fiber::yield(); total_counter++; }
 	}
 
 	volatile uint32_t f3counter{0};

diff --git a/examples/generic/fiber/main.cpp b/examples/generic/fiber/main.cpp
@@ -26,14 +26,14 @@ void
 fiber_function1()
 {
 	MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-	while (++f1counter < cycles) { modm::fiber::yield(); total_counter++; }
+	while (++f1counter < cycles) { modm::this_fiber::yield(); total_counter++; }
 }
 
 void
 fiber_function2(uint32_t cyc)
 {
 	MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-	while (++f2counter < cyc) { modm::fiber::yield(); total_counter++; }
+	while (++f2counter < cyc) { modm::this_fiber::yield(); total_counter++; }
 }
 
 struct Test
@@ -42,23 +42,23 @@ struct Test
 	fiber_function3()
 	{
 		MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-		while (++f3counter < cycles) { modm::fiber::yield(); total_counter++; }
+		while (++f3counter < cycles) { modm::this_fiber::yield(); total_counter++; }
 	}
 
 	void
 	fiber_function4(uint32_t cyc)
 	{
 		MODM_LOG_INFO << MODM_FILE_INFO << modm::endl;
-		while (++f4counter < cyc) { modm::fiber::yield(); total_counter++; }
+		while (++f4counter < cyc) { modm::this_fiber::yield(); total_counter++; }
 	}
 
 	volatile uint32_t f3counter{0};
 	volatile uint32_t f4counter{0};
 } test;
 
 // Single purpose fibers to time the yield
-modm_faststack modm::Fiber<> fiber_y1([](){ modm::fiber::yield();  counter.stop(); });
-modm_faststack modm::Fiber<> fiber_y2([](){ counter.start(); modm::fiber::yield(); });
+modm_faststack modm::Fiber<> fiber_y1([](){ modm::this_fiber::yield();  counter.stop(); });
+modm_faststack modm::Fiber<> fiber_y2([](){ counter.start(); modm::this_fiber::yield(); });
 
 modm_faststack modm::Fiber<> fiber1(fiber_function1, modm::fiber::Start::Later);
 modm_faststack modm::Fiber<> fiber2([](){ fiber_function2(cycles); }, modm::fiber::Start::Later);
@@ -71,12 +71,12 @@ extern modm::Fiber<> fiber_pong;
 extern modm::Fiber<> fiber_ping;
 modm_faststack modm::Fiber<> fiber_ping([](){
 	MODM_LOG_INFO << "ping = " << fiber_ping.stack_usage() << modm::endl;
-	modm::fiber::sleep(1s);
+	modm::this_fiber::sleep_for(1s);
 	fiber_pong.start();
 }, modm::fiber::Start::Later);
 modm_faststack modm::Fiber<> fiber_pong([](){
 	MODM_LOG_INFO << "pong = " << fiber_pong.stack_usage() << modm::endl;
-	modm::fiber::sleep(1s);
+	modm::this_fiber::sleep_for(1s);
 	fiber_ping.start();
 }, modm::fiber::Start::Later);
 

diff --git a/examples/linux/fiber/main.cpp b/examples/linux/fiber/main.cpp
@@ -17,7 +17,7 @@ void hello()
 	for(int ii=0; ii<10; ii++)
 	{
 		MODM_LOG_INFO << "Hello ";
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 	}
 }
 
@@ -28,7 +28,7 @@ struct Test
 		for(int ii=0; ii<10; ii++)
 		{
 			MODM_LOG_INFO << arg << modm::endl;
-			modm::fiber::yield();
+			modm::this_fiber::yield();
 		}
 	}
 } test;

diff --git a/examples/rp_pico/fiber/main.cpp b/examples/rp_pico/fiber/main.cpp
@@ -42,7 +42,7 @@ fiber_function1(CoreData& d)
 {
 	while (++d.f1counter < cycles)
 	{
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 		d.total_counter++;
 	}
 }
@@ -52,7 +52,7 @@ fiber_function2(CoreData& d)
 {
 	while (++d.f2counter < cycles)
 	{
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 		d.total_counter++;
 	}
 }

diff --git a/examples/stm32f3_discovery/rotation/main.cpp b/examples/stm32f3_discovery/rotation/main.cpp
@@ -69,7 +69,7 @@ modm_faststack modm::Fiber<> fiber_gyro([]()
 		}
 
 		// repeat every 5 ms
-		modm::fiber::sleep(5ms);
+		modm::this_fiber::sleep_for(5ms);
 	}
 });
 
@@ -78,7 +78,7 @@ modm_faststack modm::Fiber<> fiber_blinky([]()
 	while (true)
 	{
 		Board::LedSouth::toggle();
-		modm::fiber::sleep(1s);
+		modm::this_fiber::sleep_for(1s);
 	}
 });
 

diff --git a/examples/stm32f469_discovery/touchscreen/main.cpp b/examples/stm32f469_discovery/touchscreen/main.cpp
@@ -96,7 +96,7 @@ modm_faststack modm::Fiber<> fiber_blinky([]()
 	while(true)
 	{
 		Board::LedGreen::toggle();
-		modm::fiber::sleep(20ms);
+		modm::this_fiber::sleep_for(20ms);
 	}
 });
 

diff --git a/src/modm/driver/inertial/bmi088_impl.hpp b/src/modm/driver/inertial/bmi088_impl.hpp
@@ -225,7 +225,7 @@ void
 Bmi088<Transport>::timerWait()
 {
 	while (timer_.isArmed()) {
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 	}
 }
 

diff --git a/src/modm/driver/inertial/bmi088_transport_impl.hpp b/src/modm/driver/inertial/bmi088_transport_impl.hpp
@@ -57,7 +57,7 @@ Bmi088SpiTransport<SpiMaster, AccCs, GyroCs>::readRegisters(uint8_t startReg,
 	}
 
 	while (!this->acquireMaster()) {
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 	}
 	Cs::reset();
 
@@ -95,7 +95,7 @@ bool
 Bmi088SpiTransport<SpiMaster, AccCs, GyroCs>::writeRegister(uint8_t reg, uint8_t data)
 {
 	while (!this->acquireMaster()) {
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 	}
 	Cs::reset();
 

diff --git a/src/modm/platform/spi/at90_tiny_mega/spi_master.cpp.in b/src/modm/platform/spi/at90_tiny_mega/spi_master.cpp.in
@@ -45,7 +45,7 @@ modm::platform::SpiMaster{{ id }}::transfer(uint8_t data)
 	// start transfer by copying data into register
 	SPDR{{ id }} = data;
 
-	do modm::fiber::yield();
+	do modm::this_fiber::yield();
 	while (!(SPSR{{ id }} & (1 << SPIF{{ id }})));
 
 	return SPDR{{ id }};

diff --git a/src/modm/platform/spi/at90_tiny_mega_uart/uart_spi_master.cpp.in b/src/modm/platform/spi/at90_tiny_mega_uart/uart_spi_master.cpp.in
@@ -62,7 +62,7 @@ modm::platform::UartSpiMaster{{id}}::transfer(uint8_t data)
 %% if use_fiber
 	// wait for transmit register empty
 	while (!((UCSR{{id}}A & (1 << UDRE{{id}}))))
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 %% if not extended
 	if(dataOrder == DataOrder::MsbFirst) {
@@ -72,7 +72,7 @@ modm::platform::UartSpiMaster{{id}}::transfer(uint8_t data)
 	UDR{{id}} = data;
 
 	// wait for receive register not empty
-	do modm::fiber::yield();
+	do modm::this_fiber::yield();
 	while (!((UCSR{{id}}A & (1 << RXC{{id}}))));
 
 	data = UDR{{id}};

diff --git a/src/modm/platform/spi/rp/spi_master.cpp.in b/src/modm/platform/spi/rp/spi_master.cpp.in
@@ -30,12 +30,12 @@ modm::platform::SpiMaster{{ id }}::transfer(uint8_t data)
 {
 %% if use_fiber
 	// wait for previous transfer to finish
-	while (txFifoFull()) modm::fiber::yield();
+	while (txFifoFull()) modm::this_fiber::yield();
 
 	// start transfer by copying data into register
 	write(data);
 
-	while (rxFifoEmpty()) modm::fiber::yield();
+	while (rxFifoEmpty()) modm::this_fiber::yield();
 
 	return read();
 %% else

diff --git a/src/modm/platform/spi/rp/spi_master_dma_impl.hpp.in b/src/modm/platform/spi/rp/spi_master_dma_impl.hpp.in
@@ -123,16 +123,16 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transfer(
 	startTransfer(tx, rx, length);
 
 	while (Dma::TxChannel::isBusy() or (rx and Dma::RxChannel::isBusy()))
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	while (!txFifoEmpty() or (rx and !rxFifoEmpty()) or isBusy())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	if (!rx) {
 		// Drain RX FIFO, then wait for shifting to finish (which
 		// may be *after* TX FIFO drains), then drain RX FIFO again
 		while (!rxFifoEmpty()) read();
-		while (isBusy()) modm::fiber::yield();
+		while (isBusy()) modm::this_fiber::yield();
 
 		// Don't leave overrun flag set
 		spi{{ id }}_hw->icr = SPI_SSPICR_RORIC_BITS;

diff --git a/src/modm/platform/spi/sam/spi_master.cpp.in b/src/modm/platform/spi/sam/spi_master.cpp.in
@@ -26,14 +26,14 @@ modm::platform::SpiMaster{{ id }}::transfer(uint8_t data)
 
 	// wait for previous transfer to finish
 	while (!isTransmitDataRegisterEmpty())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// start transfer by copying data into register
 	write(data);
 
 	// wait for current transfer to finish
 	while(!isReceiveDataRegisterFull())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	return read();
 %% else

diff --git a/src/modm/platform/spi/sam_x7x/spi_master.cpp.in b/src/modm/platform/spi/sam_x7x/spi_master.cpp.in
@@ -23,14 +23,14 @@ modm::platform::SpiMaster{{ id }}::transfer(uint8_t data)
 %% if use_fiber
 	// wait for previous transfer to finish
 	while(!(SpiHal{{ id }}::readStatusFlags() & StatusFlag::TxRegisterEmpty))
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// start transfer by copying data into register
 	SpiHal{{ id }}::write(data);
 
 	// wait for current transfer to finish
 	while(!(SpiHal{{ id }}::readStatusFlags() & StatusFlag::RxRegisterFull))
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// read the received byte
 	SpiHal{{ id }}::read(data);

diff --git a/src/modm/platform/spi/stm32/spi_master.cpp.in b/src/modm/platform/spi/stm32/spi_master.cpp.in
@@ -22,14 +22,14 @@ modm::platform::SpiMaster{{ id }}::transfer(uint8_t data)
 %% if use_fiber
 	// wait for previous transfer to finish
 	while(!SpiHal{{ id }}::isTransmitRegisterEmpty())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// start transfer by copying data into register
 	SpiHal{{ id }}::write(data);
 
 	// wait for current transfer to finish
 	while(!SpiHal{{ id }}::isReceiveRegisterNotEmpty())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// read the received byte
 	SpiHal{{ id }}::read(data);

diff --git a/src/modm/platform/spi/stm32/spi_master_dma_impl.hpp.in b/src/modm/platform/spi/stm32/spi_master_dma_impl.hpp.in
@@ -61,14 +61,14 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transfer(uint
 
 	// wait for previous transfer to finish
 	while(!SpiHal{{ id }}::isTransmitRegisterEmpty())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// start transfer by copying data into register
 	SpiHal{{ id }}::write(data);
 
 	// wait for current transfer to finish
 	while(!SpiHal{{ id }}::isReceiveRegisterNotEmpty())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// read the received byte
 	SpiHal{{ id }}::read(data);
@@ -146,14 +146,14 @@ modm::platform::SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transfer(
 	{
 		if (dmaError) break;
 		else if (not dmaTransmitComplete and not dmaReceiveComplete)
-			modm::fiber::yield();
+			modm::this_fiber::yield();
 %% if "fifo" in features
 		else if (SpiHal{{ id }}::getInterruptFlags() & (SpiBase::InterruptFlag::Busy
 				| SpiBase::InterruptFlag::FifoTxLevel | SpiBase::InterruptFlag::FifoRxLevel))
 %% else
 		else if (SpiHal{{ id }}::getInterruptFlags() & SpiBase::InterruptFlag::Busy)
 %% endif
-			modm::fiber::yield();
+			modm::this_fiber::yield();
 		else break;
 	}
 

diff --git a/src/modm/platform/spi/stm32_uart/uart_spi_master.cpp.in b/src/modm/platform/spi/stm32_uart/uart_spi_master.cpp.in
@@ -31,7 +31,7 @@ modm::platform::UartSpiMaster{{ id }}::transfer(uint8_t data)
 %% if use_fiber
 	// wait for previous transfer to finish
 	while (!UsartHal{{ id }}::isTransmitRegisterEmpty())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	// start transfer by copying data into register
 	if(dataOrder == DataOrder::MsbFirst)
@@ -40,7 +40,7 @@ modm::platform::UartSpiMaster{{ id }}::transfer(uint8_t data)
 
 	// wait for current transfer to finish
 	while (!UsartHal{{ id }}::isReceiveRegisterNotEmpty())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	UsartHal{{ id }}::read(data);
 

diff --git a/src/modm/platform/spi/stm32h7/spi_master.cpp.in b/src/modm/platform/spi/stm32h7/spi_master.cpp.in
@@ -25,12 +25,12 @@ SpiMaster{{ id }}::transfer(uint8_t data)
 {
 %% if use_fiber
 	while (Hal::isTxFifoFull())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	Hal::write(data);
 
 	while (!Hal::isRxDataAvailable())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	return Hal::read();
 %% else
@@ -83,7 +83,7 @@ SpiMaster{{ id }}::transfer(
 			++rxIndex;
 		}
 		if (rxIndex < length) {
-			modm::fiber::yield();
+			modm::this_fiber::yield();
 		}
 	}
 %% else

diff --git a/src/modm/platform/spi/stm32h7/spi_master_dma_impl.hpp.in b/src/modm/platform/spi/stm32h7/spi_master_dma_impl.hpp.in
@@ -66,7 +66,7 @@ SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transfer(uint8_t data)
 
 	// wait for transfer to complete
 	while (!Hal::isTransferCompleted())
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 
 	data = SpiHal{{ id }}::read();
 	finishTransfer();
@@ -174,7 +174,7 @@ SpiMaster{{ id }}_Dma<DmaChannelRx, DmaChannelTx>::transfer(
 				break;
 			}
 		}
-		modm::fiber::yield();
+		modm::this_fiber::yield();
 	}
 	finishTransfer();
 %% else