Postmigration Developments
Migration developments in Extra Tabulo 0 (ET0) are published which focus on new design with CEC1702 Cortex-M4F ISA and circuitry. Existing STM32F and STM32L Cortex-M4 ISA revisions are maintained in a separate branch named revstm.
Feature Changes
This hardware revision removes several features until migration testing stabilises. These include BMA accelerometer supported tap detection, ambient light logical intrusion detection, AES CCC EPROM storage acceleration, and capacitive touch support with LED backlight.
Secure Element Integration
The previously I²C connected ATECC608A is now integrated to the MCU's interdie security blocks as described in the ROM addendum paragraph 4.2.
Power Circuits
Two main power regulators are available with the dedicated LDO cut from upstream circuits with a jumper. Should the UART bridge's voltage conversion feature prove inadequate, the dedicated LDO can quickly take it's place.
Panelisation
A new panel design includes Stencil8 NPTH drills as well as reducing boards to six up for small PnP machines.
Display Interface
Both 24 pin and 30 pin FPC connectors are available, although only one practically fits on the board surface, so the new 24 pin format is absent.
Missing Switches
A mechanical detection switch and a planned boot switch are not populated until migration work proves their utility.
External Storage
As recommended, a 16 or 64 megabit SQI flash memory is used to serve as the main program storage.
One Time Programming
A OTP voltage input is provided with a simple jumper rather than a proper switch interface pending user interface testing. A 1V59 regulator is intentionally replaced with a easier to design and use 1V5 regulator pending power testing.
Programming Interfaces
Both SWD (use a JTAG programmer) and SPI interfaces are terminated with the appropriate headers. The SPI connector assumes Dediprog pin assignments and both regular one mil and tag connect hardware terminates the SWD connectors.