Adding additional snippets

[jessicarod7]

This issue will be associated with a pull request to add more snippets to System Verilog, and potentially Verilog. This PDF is one of the sources I'll be using. I'll also add the snippets suggested in #94 and #99.

I'll also look into adjusting prefixes and snippet names to make them easier to find (for example, always_ff as a prefix will match both ff and alway). A full list of modified snippets will be included in the pull request.

Here is an continuously updated checklist of snippets to be added:

• Verilog
  • always @(negedge clk)
  • localparam
  • generate
  • genvar
  • casez/casex
  • Compiler directives
    • ifdef/ifndef/undef
    • elsif/endif
    • default_nettype
  • signed
  • integer
• SystemVerilog
  • package
  • import
  • modport
  • shortint/longint