Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

Merge in late fixes to prepare for the 6.6 net-next PR.

No conflicts.

Signed-off-by: Paolo Abeni <pabeni@redhat.com>

Documentation/devicetree/bindings/net/dsa/marvell.txt

@@ -20,7 +20,7 @@ which is at a different MDIO base address in different switch families.
  6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
  6341, 6350, 6351, 6352
 - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
- 6163, 6190, 6190X, 6191, 6290, 6390, 6390X
+ 6190, 6190X, 6191, 6290, 6361, 6390, 6390X
 - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
  6220, 6250
 

drivers/net/arcnet/arcnet.c

@@ -464,7 +464,7 @@ static void arcnet_reply_tasklet(struct tasklet_struct *t)
 
  ret = sock_queue_err_skb(sk, ackskb);
  if (ret)
- kfree_skb(ackskb);
+ dev_kfree_skb_irq(ackskb);
 
  local_irq_enable();
 };

drivers/net/ethernet/amd/pds_core/core.c

@@ -464,7 +464,8 @@ void pdsc_teardown(struct pdsc *pdsc, bool removing)
 {
  int i;
 
- pdsc_devcmd_reset(pdsc);
+ if (!pdsc->pdev->is_virtfn)
+ pdsc_devcmd_reset(pdsc);
  pdsc_qcq_free(pdsc, &pdsc->notifyqcq);
  pdsc_qcq_free(pdsc, &pdsc->adminqcq);
 
@@ -524,7 +525,8 @@ static void pdsc_fw_down(struct pdsc *pdsc)
  }
 
  /* Notify clients of fw_down */
- devlink_health_report(pdsc->fw_reporter, "FW down reported", pdsc);
+ if (pdsc->fw_reporter)
+ devlink_health_report(pdsc->fw_reporter, "FW down reported", pdsc);
  pdsc_notify(PDS_EVENT_RESET, &reset_event);
 
  pdsc_stop(pdsc);
@@ -554,8 +556,9 @@ static void pdsc_fw_up(struct pdsc *pdsc)
 
  /* Notify clients of fw_up */
  pdsc->fw_recoveries++;
- devlink_health_reporter_state_update(pdsc->fw_reporter,
- DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
+ if (pdsc->fw_reporter)
+ devlink_health_reporter_state_update(pdsc->fw_reporter,
+ DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
  pdsc_notify(PDS_EVENT_RESET, &reset_event);
 
  return;

drivers/net/ethernet/amd/pds_core/dev.c

@@ -121,7 +121,7 @@ static const char *pdsc_devcmd_str(int opcode)
  }
 }
 
-static int pdsc_devcmd_wait(struct pdsc *pdsc, int max_seconds)
+static int pdsc_devcmd_wait(struct pdsc *pdsc, u8 opcode, int max_seconds)
 {
  struct device *dev = pdsc->dev;
  unsigned long start_time;
@@ -131,9 +131,6 @@ static int pdsc_devcmd_wait(struct pdsc *pdsc, int max_seconds)
  int done = 0;
  int err = 0;
  int status;
- int opcode;
-
- opcode = ioread8(&pdsc->cmd_regs->cmd.opcode);
 
  start_time = jiffies;
  max_wait = start_time + (max_seconds * HZ);
@@ -180,10 +177,10 @@ int pdsc_devcmd_locked(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
 
  memcpy_toio(&pdsc->cmd_regs->cmd, cmd, sizeof(*cmd));
  pdsc_devcmd_dbell(pdsc);
- err = pdsc_devcmd_wait(pdsc, max_seconds);
+ err = pdsc_devcmd_wait(pdsc, cmd->opcode, max_seconds);
  memcpy_fromio(comp, &pdsc->cmd_regs->comp, sizeof(*comp));
 
- if (err == -ENXIO || err == -ETIMEDOUT)
+ if ((err == -ENXIO || err == -ETIMEDOUT) && pdsc->wq)
  queue_work(pdsc->wq, &pdsc->health_work);
 
  return err;

drivers/net/ethernet/amd/pds_core/devlink.c

@@ -10,6 +10,9 @@ pdsc_viftype *pdsc_dl_find_viftype_by_id(struct pdsc *pdsc,
 {
  int vt;
 
+ if (!pdsc->viftype_status)
+ return NULL;
+
  for (vt = 0; vt < PDS_DEV_TYPE_MAX; vt++) {
  if (pdsc->viftype_status[vt].dl_id == dl_id)
  return &pdsc->viftype_status[vt];

drivers/net/ethernet/broadcom/tg3.c

@@ -17794,10 +17794,7 @@ static int tg3_init_one(struct pci_dev *pdev,
  tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
 
  tnapi->int_mbox = intmbx;
- if (i <= 4)
- intmbx += 0x8;
- else
- intmbx += 0x4;
+ intmbx += 0x8;
 
  tnapi->consmbox = rcvmbx;
  tnapi->prodmbox = sndmbx;

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

@@ -131,6 +131,8 @@ static void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
  case READ_TIME:
  cmd_val |= GLTSYN_CMD_READ_TIME;
  break;
+ case ICE_PTP_NOP:
+ break;
  }
 
  wr32(hw, GLTSYN_CMD, cmd_val);
@@ -1226,18 +1228,18 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
 }
 
 /**
- * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command
+ * ice_ptp_write_port_cmd_e822 - Prepare a single PHY port for a timer command
  * @hw: pointer to HW struct
  * @port: Port to which cmd has to be sent
  * @cmd: Command to be sent to the port
  *
  * Prepare the requested port for an upcoming timer sync command.
  *
- * Note there is no equivalent of this operation on E810, as that device
- * always handles all external PHYs internally.
+ * Do not use this function directly. If you want to configure exactly one
+ * port, use ice_ptp_one_port_cmd() instead.
  */
 static int
-ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
+ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
 {
  u32 cmd_val, val;
  u8 tmr_idx;
@@ -1261,6 +1263,8 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
  case ADJ_TIME_AT_TIME:
  cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
  break;
+ case ICE_PTP_NOP:
+ break;
  }
 
  /* Tx case */
@@ -1306,6 +1310,39 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)
  return 0;
 }
 
+/**
+ * ice_ptp_one_port_cmd - Prepare one port for a timer command
+ * @hw: pointer to the HW struct
+ * @configured_port: the port to configure with configured_cmd
+ * @configured_cmd: timer command to prepare on the configured_port
+ *
+ * Prepare the configured_port for the configured_cmd, and prepare all other
+ * ports for ICE_PTP_NOP. This causes the configured_port to execute the
+ * desired command while all other ports perform no operation.
+ */
+static int
+ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
+ enum ice_ptp_tmr_cmd configured_cmd)
+{
+ u8 port;
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ enum ice_ptp_tmr_cmd cmd;
+ int err;
+
+ if (port == configured_port)
+ cmd = configured_cmd;
+ else
+ cmd = ICE_PTP_NOP;
+
+ err = ice_ptp_write_port_cmd_e822(hw, port, cmd);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
 /**
  * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command
  * @hw: pointer to the HW struct
@@ -1322,7 +1359,7 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
  for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
  int err;
 
- err = ice_ptp_one_port_cmd(hw, port, cmd);
+ err = ice_ptp_write_port_cmd_e822(hw, port, cmd);
  if (err)
  return err;
  }
@@ -2252,6 +2289,9 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
  if (err)
  goto err_unlock;
 
+ /* Do not perform any action on the main timer */
+ ice_ptp_src_cmd(hw, ICE_PTP_NOP);
+
  /* Issue the sync to activate the time adjustment */
  ice_ptp_exec_tmr_cmd(hw);
 
@@ -2372,6 +2412,9 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
  if (err)
  return err;
 
+ /* Do not perform any action on the main timer */
+ ice_ptp_src_cmd(hw, ICE_PTP_NOP);
+
  ice_ptp_exec_tmr_cmd(hw);
 
  err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
@@ -2847,6 +2890,8 @@ static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
  case ADJ_TIME_AT_TIME:
  cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
  break;
+ case ICE_PTP_NOP:
+ return 0;
  }
 
  /* Read, modify, write */

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

@@ -9,7 +9,8 @@ enum ice_ptp_tmr_cmd {
  INIT_INCVAL,
  ADJ_TIME,
  ADJ_TIME_AT_TIME,
- READ_TIME
+ READ_TIME,
+ ICE_PTP_NOP,
 };
 
 enum ice_ptp_serdes {

drivers/net/ethernet/intel/igb/igb_main.c

@@ -4814,6 +4814,10 @@ void igb_configure_rx_ring(struct igb_adapter *adapter,
 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
  struct igb_ring *rx_ring)
 {
+#if (PAGE_SIZE < 8192)
+ struct e1000_hw *hw = &adapter->hw;
+#endif
+
  /* set build_skb and buffer size flags */
  clear_ring_build_skb_enabled(rx_ring);
  clear_ring_uses_large_buffer(rx_ring);
@@ -4824,10 +4828,9 @@ static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
  set_ring_build_skb_enabled(rx_ring);
 
 #if (PAGE_SIZE < 8192)
- if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
- return;
-
- set_ring_uses_large_buffer(rx_ring);
+ if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB ||
+ rd32(E1000_RCTL) & E1000_RCTL_SBP)
+ set_ring_uses_large_buffer(rx_ring);
 #endif
 }
 

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

@@ -355,8 +355,8 @@ int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,
 
 void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)
 {
+ u64 cfg, pfc_class_mask_cfg;
  rpm_t *rpm = rpmd;
- u64 cfg;
 
  /* ALL pause frames received are completely ignored */
  cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
@@ -380,9 +380,11 @@ void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)
  rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL);
 
  /* Disable all PFC classes */
- cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL);
+ pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
+ RPMX_CMRX_PRT_CBFC_CTL;
+ cfg = rpm_read(rpm, lmac_id, pfc_class_mask_cfg);
  cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg);
- rpm_write(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL, cfg);
+ rpm_write(rpm, lmac_id, pfc_class_mask_cfg, cfg);
 }
 
 int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat)
@@ -605,8 +607,11 @@ int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 p
  if (!is_lmac_valid(rpm, lmac_id))
  return -ENODEV;
 
+ pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
+ RPMX_CMRX_PRT_CBFC_CTL;
+
  cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
- class_en = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL);
+ class_en = rpm_read(rpm, lmac_id, pfc_class_mask_cfg);
  pfc_en |= FIELD_GET(RPM_PFC_CLASS_MASK, class_en);
 
  if (rx_pause) {
@@ -635,10 +640,6 @@ int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 p
  cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;
 
  rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
-
- pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL :
- RPMX_CMRX_PRT_CBFC_CTL;
-
  rpm_write(rpm, lmac_id, pfc_class_mask_cfg, class_en);
 
  return 0;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

@@ -806,6 +806,7 @@ void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq)
 
  mutex_unlock(&pfvf->mbox.lock);
 }
+EXPORT_SYMBOL(otx2_txschq_free_one);
 
 void otx2_txschq_stop(struct otx2_nic *pfvf)
 {
@@ -1434,7 +1435,7 @@ int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
  }
 
  pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP;
- pp_params.pool_size = numptrs;
+ pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs);
  pp_params.nid = NUMA_NO_NODE;
  pp_params.dev = pfvf->dev;
  pp_params.dma_dir = DMA_FROM_DEVICE;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c

@@ -70,7 +70,7 @@ static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio)
  * link config level. These rest of the scheduler can be
  * same as hw.txschq_list.
  */
- for (lvl = 0; lvl < pfvf->hw.txschq_link_cfg_lvl; lvl++)
+ for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++)
  req->schq[lvl] = 1;
 
  rc = otx2_sync_mbox_msg(&pfvf->mbox);
@@ -83,7 +83,7 @@ static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio)
  return PTR_ERR(rsp);
 
  /* Setup transmit scheduler list */
- for (lvl = 0; lvl < pfvf->hw.txschq_link_cfg_lvl; lvl++) {
+ for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++) {
  if (!rsp->schq[lvl])
  return -ENOSPC;
 
@@ -125,19 +125,12 @@ int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf)
 
 static int otx2_pfc_txschq_stop_one(struct otx2_nic *pfvf, u8 prio)
 {
- struct nix_txsch_free_req *free_req;
+ int lvl;
 
- mutex_lock(&pfvf->mbox.lock);
  /* free PFC TLx nodes */
- free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
- if (!free_req) {
- mutex_unlock(&pfvf->mbox.lock);
- return -ENOMEM;
- }
-
- free_req->flags = TXSCHQ_FREE_ALL;
- otx2_sync_mbox_msg(&pfvf->mbox);
- mutex_unlock(&pfvf->mbox.lock);
+ for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++)
+ otx2_txschq_free_one(pfvf, lvl,
+ pfvf->pfc_schq_list[lvl][prio]);
 
  pfvf->pfc_alloc_status[prio] = false;
  return 0;

drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h

@@ -23,6 +23,8 @@
 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
 #define OTX2_MIN_MTU 60
 
+#define OTX2_PAGE_POOL_SZ 2048
+
 #define OTX2_MAX_GSO_SEGS 255
 #define OTX2_MAX_FRAGS_IN_SQE 9